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Processor power dissipation

(Redirected from CPU electrical consumption)

Processor power dissipation or processing unit power dissipation is the process in which computer processors consume electrical energy, and dissipate this energy in the form of heat due to the resistance in the electronic circuits.

Photos of heatsinks

Power management

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See also: Variable TDP

Designing CPUs that perform tasks efficiently without overheating is a major consideration of nearly all CPU manufacturers to date. Historically, early CPUs implemented with vacuum tubes consumed power on the order of many kilowatts. Current CPUs in general-purpose personal computers, such as desktops and laptops, consume power in the order of tens to hundreds of watts. Some other CPU implementations use very little power; for example, the CPUs in mobile phones often use just a few watts of electricity,[1] while some microcontrollers used in embedded systems may consume only a few milliwatts or even as little as a few microwatts.

There are a number of engineering reasons for this pattern:

  • For a given CPU core, energy usage will scale up as its clock rate increases. Reducing the clock rate or undervolting usually reduces energy consumption; it is also possible to undervolt the microprocessor while keeping the clock rate the same.[2]
  • New features generally require more transistors, each of which uses power. Turning unused areas off saves energy, such as through clock gating.
  • As a processor model's design matures, smaller transistors, lower-voltage structures, and design experience may reduce energy consumption.

Processor manufacturers usually release two power consumption numbers for a CPU:

  • typical thermal power, which is measured under normal load (for instance, AMD's average CPU power)
  • maximum thermal power, which is measured under a worst-case load

For example, the Pentium 4 2.8 GHz has a 68.4 W typical thermal power and 85 W maximum thermal power. When the CPU is idle, it will draw far less than the typical thermal power. Datasheets normally contain the thermal design power (TDP), which is the maximum amount of heat generated by the CPU, which the cooling system in a computer is required to dissipate. Both Intel and Advanced Micro Devices (AMD) have defined TDP as the maximum heat generation for thermally significant periods, while running worst-case non-synthetic workloads; thus, TDP is not reflecting the actual maximum power of the processor. This ensures the computer will be able to handle essentially all applications without exceeding its thermal envelope, or requiring a cooling system for the maximum theoretical power (which would cost more but in favor of extra headroom for processing power).[3][4]

In many applications, the CPU and other components are idle much of the time, so idle power contributes significantly to overall system power usage. When the CPU uses power management features to reduce energy use, other components, such as the motherboard and chipset, take up a larger proportion of the computer's energy. In applications where the computer is often heavily loaded, such as scientific computing, performance per watt (how much computing the CPU does per unit of energy) becomes more significant.

CPUs typically use a significant portion of the power consumed by the computer. Other major uses include fast video cards, which contain graphics processing units, and power supplies. In laptops, the LCD's backlight also uses a significant portion of overall power. While energy-saving features have been instituted in personal computers for when they are idle, the overall consumption of today's high-performance CPUs is considerable. This is in strong contrast with the much lower energy consumption of CPUs designed for low-power devices.

Sources

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There are several factors contributing to the CPU power consumption; they include dynamic power consumption, short-circuit power consumption, and power loss due to transistor leakage currents:

 

The dynamic power consumption originates from the activity of logic gates inside a CPU. When the logic gates toggle, energy is flowing as the capacitors inside them are charged and discharged. The dynamic power consumed by a CPU is approximately proportional to the CPU frequency, and to the square of the CPU voltage:[5]

 

where C is the switched load capacitance, f is frequency, V is voltage.[6]

When logic gates toggle, some transistors inside may change states. As this takes a finite amount of time, it may happen that for a very brief amount of time some transistors are conducting simultaneously. A direct path between the source and ground then results in some short-circuit power loss ( ). The magnitude of this power is dependent on the logic gate, and is rather complex to model on a macro level.

Power consumption due to leakage power ( ) emanates at a micro-level in transistors. Small amounts of currents are always flowing between the differently doped parts of the transistor. The magnitude of these currents depend on the state of the transistor, its dimensions, physical properties and sometimes temperature. The total amount of leakage currents tends to inflate for increasing temperature and decreasing transistor sizes.

Both dynamic and short-circuit power consumption are dependent on the clock frequency, while the leakage current is dependent on the CPU supply voltage. It has been shown that the energy consumption of a program shows convex energy behavior, meaning that there exists an optimal CPU frequency at which energy consumption is minimal for the work done.[7]

Reduction

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Power consumption can be reduced in several ways,[citation needed] including the following:

  • Voltage reduction – dual-voltage CPUs, dynamic voltage scaling, undervolting, etc.
  • Frequency reduction – underclocking, dynamic frequency scaling, etc.
  • Capacitance reduction – increasingly integrated circuits that replace PCB traces between two chips with relatively lower-capacitance on-chip metal interconnect between two sections of a single integrated chip; low-κ dielectric, etc.
  • Power gating techniques such as clock gating and globally asynchronous locally synchronous, which can be thought of as reducing the capacitance switched on each clock tick, or can be thought of as locally reducing the clock frequency in some sections of the chip.
  • Various techniques to reduce the switching activity – number of transitions the CPU drives into off-chip data buses, such as non-multiplexed address bus, bus encoding such as Gray code addressing,[8] or value cache encoding such as power protocol.[9] Sometimes an "activity factor" (A) is put into the above equation to reflect activity.[10]
  • Sacrificing transistor density for higher frequencies.
  • Layering heat-conduction zones within the CPU framework ("Christmassing the Gate").
  • Recycling at least some of that energy stored in the capacitors (rather than dissipating it as heat in transistors) – adiabatic circuit, energy recovery logic, etc.
  • Optimizing machine code - by implementing compiler optimizations that schedules clusters of instructions using common components, the CPU power used to run an application can be significantly reduced.[11]

Clock frequencies and multi-core chip designs

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Historically, processor manufacturers consistently delivered increases in clock rates and instruction-level parallelism, so that single-threaded code executed faster on newer processors with no modification.[12] More recently, in order to manage CPU power dissipation, processor makers favor multi-core chip designs, thus software needs to be written in a multi-threaded or multi-process manner to take full advantage of such hardware. Many multi-threaded development paradigms introduce overhead, and will not see a linear increase in speed when compared to the number of processors. This is particularly true while accessing shared or dependent resources, due to lock contention. This effect becomes more noticeable as the number of processors increases.

Recently, IBM has been exploring ways to distribute computing power more efficiently by mimicking the distributional properties of the human brain.[13]

Processor overheating

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Processors can be damaged from overheating, but vendors protect processors with operational safeguards such as throttling and automatic shutdown. When a core exceeds the set throttle temperature, processors can reduce power to maintain a safe temperature level and if the processor is unable to maintain a safe operating temperature through throttling actions, it will automatically shut down to prevent permanent damage.[14]

See also

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References

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  1. ^ Zhang, Yifan; Liu, Yunxin; Zhuang, Li; Liu, Xuanzhe; Zhao, Feng; Li, Qun. Accurate CPU Power Modeling for Multicore Smartphones (Report). Microsoft Research. MSR-TR-2015-9.
  2. ^ Cutress, Ian (2012-04-23). "Undervolting and Overclocking on Ivy Bridge". anandtech.com.
  3. ^ Chin, Mike (2004-06-15). "Athlon 64 for Quiet Power". silentpcreview.com. p. 3. Retrieved 2013-12-21. Thermal Design Power (TDP) should be used for processor thermal solution design targets. The TDP is not the maximum power that the processor can dissipate.
  4. ^ Cunningham, Andrew (2013-01-14). "The technical details behind Intel's 7 Watt Ivy Bridge CPUs". Ars Technica. Retrieved 2013-01-14. In Intel's case, a specified chip's TDP has less to do with the amount of power a chip needs to use (or can use) and more to do with the amount of power the computer's fan and heatsink need to be able to dissipate while the chip is under sustained load. Actual power usage can be higher or (much) lower than TDP, but the figure is intended to give guidance to engineers designing cooling solutions for their products.
  5. ^ "Enhanced Intel SpeedStep Technology for the Intel Pentium M Processor (White Paper)" (PDF). Intel Corporation. March 2004. Archived (PDF) from the original on 2015-08-12. Retrieved 2013-12-21.
  6. ^ Jan M. Rabaey; Massoud Pedram; editors. "Low Power Design Methodologies". 2012. p. 133.
  7. ^ De Vogeleer, Karel; Memmi, Gerard; Jouvelot, Pierre; Coelho, Fabien (2013-09-09). "The Energy/Frequency Convexity Rule: Modeling and Experimental Validation on Mobile Devices". arXiv:1401.4655 [cs.OH].
  8. ^ Su, Ching-Long; Tsui, Chi-Ying; Despain, Alvin M. (1994). Low Power Architecture Design and Compilation Techniques for High-Performance Processors (PDF) (Report). Advanced Computer Architecture Laboratory. ACAL-TR-94-01.
  9. ^ Basu, K.; Choudhary, A.; Pisharath, J.; Kandemir, M. (2002). "Power protocol: Reducing power dissipation on off-chip data buses". 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings (PDF). pp. 345–355. CiteSeerX 10.1.1.115.9946. doi:10.1109/MICRO.2002.1176262. ISBN 978-0-7695-1859-6. S2CID 18811466.
  10. ^ K. Moiseev, A. Kolodny and S. Wimer (September 2008). "Timing-aware power-optimal ordering of signals". ACM Transactions on Design Automation of Electronic Systems. 13 (4): 1–17. doi:10.1145/1391962.1391973. S2CID 18895687.
  11. ^ Al-Khatib, Zaid; Abdi, Samar (2015-04-13). "Operand-Value-Based Modeling of Dynamic Energy Consumption of Soft Processors in FPGA". Applied Reconfigurable Computing. Lecture Notes in Computer Science. Vol. 9040. Springer, Cham. pp. 65–76. doi:10.1007/978-3-319-16214-0_6. ISBN 978-3-319-16213-3.
  12. ^ Sutter, Herb (2005). "The Free Lunch Is Over: A Fundamental Turn Toward Concurrency in Software". Dr. Dobb's Journal. 30 (3).
  13. ^ Johnson, R. Colin (2011-08-18). "IBM demos cognitive computer chips". EE Times. Retrieved 2011-10-01.
  14. ^ "Frequently Asked Questions About Temperature for Intel® Processors".

Further reading

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