Channel router

A channel router is a specific variety of router for integrated circuits. Normally using two layers of interconnect, it must connect the specified pins on the top and bottom of the channel. Specified nets must also be brought out to the left and right of the channel, but may be brought out in any order. The height of the channel is not specified - the router computes what height is needed.

Figure 1: A channel routing problem. The numbered pins on the top and bottom of the channel must be connected. The nets specified on the left and right of the channel must be brought to that end of the channel

Figure 2: A solution to the channel routing problem shown above. Solutions are not unique, and this is just one of the many possible.

The density of a channel, defined for every x within the channel, is the number of nets that appear on both the left and right of a vertical line at that x. The maximum density is a lower bound on the height of the channel. A "cyclic constraint" occurs when two pins occur in the same column (but with different orders) in at least two columns. In the example shown, nets 1 and 3 suffer from cyclic constraints. This can only be solved by "doglegs" as shown on net 1 of the example.

Channel routers were one of the first forms of routers for integrated circuits,^[1] and were heavily used for many years, with YACR^[2] perhaps the best known program. However, modern chips have many more than 2 interconnect layers. Although the effort was made to extend channel routers to more layers,^[3]^[4] this approach was never very popular, since it did not work well with over-the-cell routing where pins are not movable. In recent years, area routers have in general taken over.

References

^ Feller, A. 1976. Automatic layout of low-cost quick-turnaround random-logic custom LSI devices . In Proceedings of the 13th Conference on Design Automation (San Francisco, California, United States, June 28–30, 1976). DAC '76. ACM Press, New York, NY, 79-85.
^ Reed, J., Sangiovanni-Vincentelli, A., Santomauro, M.; A New Symbolic Channel Router: YACR2, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol.4, Iss.3, July 1985 Pages: 208- 219
^ Braun, D., Burns, J., Davadas, S., Ma, H. K., Mayaram, K., Romeo, F., and Sangiovanni-Vincentelli, A. 1986. Chameleon: a new multi-layer channel router. In Proceedings of the 23rd ACM/IEEE Conference on Design Automation (Las Vegas, Nevada, United States). Annual ACM IEEE Design Automation Conference. IEEE Press, Piscataway, NJ, 495-502.
^ Fang, S., Feng, W., and Lee, S. 1992. A new efficient approach to multilayer channel routing problem . In Proceedings of the 29th ACM/IEEE Conference on Design Automation (Anaheim, California, United States, June 08–12, 1992). Annual ACM IEEE Design Automation Conference. IEEE Computer Society Press, Los Alamitos, CA, 579-584

[1] Feller, A. 1976. Automatic layout of low-cost quick-turnaround random-logic custom LSI devices . In Proceedings of the 13th Conference on Design Automation (San Francisco, California, United States, June 28–30, 1976). DAC '76. ACM Press, New York, NY, 79-85.

[2] Reed, J., Sangiovanni-Vincentelli, A., Santomauro, M.; A New Symbolic Channel Router: YACR2, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol.4, Iss.3, July 1985 Pages: 208- 219

[3] Braun, D., Burns, J., Davadas, S., Ma, H. K., Mayaram, K., Romeo, F., and Sangiovanni-Vincentelli, A. 1986. Chameleon: a new multi-layer channel router. In Proceedings of the 23rd ACM/IEEE Conference on Design Automation (Las Vegas, Nevada, United States). Annual ACM IEEE Design Automation Conference. IEEE Press, Piscataway, NJ, 495-502.

[4] Fang, S., Feng, W., and Lee, S. 1992. A new efficient approach to multilayer channel routing problem . In Proceedings of the 29th ACM/IEEE Conference on Design Automation (Anaheim, California, United States, June 08–12, 1992). Annual ACM IEEE Design Automation Conference. IEEE Computer Society Press, Los Alamitos, CA, 579-584

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