Pass transistor logic

In electronics, pass transistor logic (PTL) describes several logic families used in the design of integrated circuits. It reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. Transistors are used as switches to pass logic levels between nodes of a circuit, instead of as switches connected directly to supply voltages.^[1] This reduces the number of active devices, but has the disadvantage that the difference of the voltage between high and low logic levels decreases at each stage (since pass transistors have some resistance and do not provide level restoration). Each transistor in series is less saturated at its output than at its input.^[2] If several devices are chained in series in a logic path, a conventionally constructed gate may be required to restore the signal voltage to the full value. By contrast, conventional CMOS logic switches transistors so the output connects to one of the power supply rails (resembling an open collector scheme), so logic voltage levels in a sequential chain do not decrease. Simulation of circuits may be required to ensure adequate performance.

Applications

A six-transistor CMOS SRAM cell. M5 and M6 are bidirectional pass transistors.

a 10-transistor CMOS gated D latch, similar to the ones in the CD4042 or the CD74HC75 integrated circuits.

Pass transistor logic often uses fewer transistors, runs faster, and requires less power than the same function implemented with the same transistors in fully complementary CMOS logic.^[3]

XOR has the worst-case Karnaugh map—if implemented from simple gates, it requires more transistors than any other function. Back when transistors were more expensive, designers of the Z80 and many other chips were motivated to save a few transistors by implementing the XOR using pass-transistor logic rather than simple gates.^[4]

Basic principles of pass transistor circuits

MOSFET pass transistors are electronic switches that turn on or off the path between their drain and source depending on their gate's voltage signal (for instance the clock signal in the SRAM cell or gated D latch).

Because pass transistors do not provide level restoration and because their conducting path has a small non-zero resistance, there is increased RC delay for charging the next logic stage's input capacitance (which includes parasitic capacitance in addition to the next stage's gate capacitance) towards valid logic-high or logic-low voltage levels.

Simulation of circuits may be required to ensure adequate performance.

Complementary pass transistor logic

Some authors use the term "complementary pass transistor logic" to indicate a style of implementing logic gates that uses transmission gates composed of both NMOS and PMOS pass transistors.^[5]

Other authors use the term "complementary pass transistor logic" (CPL) to indicate a style of implementing logic gates where each gate consists of a NMOS-only pass transistor network, followed by a CMOS output inverter.^[6]^[7]^[8]

Other authors use the term "complementary pass transistor logic" (CPL) to indicate a style of implementing logic gates using dual-rail encoding. Every CPL gate has two output wires, both the positive signal and the complementary signal, eliminating the need for inverters.^[9]^[10]^[11]

Complementary pass transistor logic or "Differential pass transistor logic" refers to a logic family which is designed for certain advantage. It is common to use this logic family for multiplexers and latches.^{[citation needed]}

CPL uses series transistors to select between possible inverted output values of the logic, the output of which drives an inverter The CMOS transmission gates consist of nMOS and pMOS transistor connected in parallel.

Other forms

Static and dynamic types of pass transistor logic exist, with differing properties with respect to speed, power and low-voltage operation.^[12] As integrated circuit supply voltages decrease, the disadvantages of pass transistor logic become more significant; the threshold voltage of transistors becomes large compared to the supply voltage, severely limiting the number of sequential stages. Because complementary inputs are often required to control pass transistors, additional logic stages are required.

References

^ Segura, Jaume; Hawkins, Charles F. (2004). CMOS electronics: how it works, how it fails. Wiley-IEEE. p. 132. ISBN 0-471-47669-2.
^ Maxfield, Clive (2008). Bebop to the boolean boogie: an unconventional guide to electronics. Newnes. pp. 423–6. ISBN 978-1-85617-507-4.
^ Norimitsu Sako. "Patent US7171636: Pass-transistor logic circuit and a method of designing thereof". 'It is known in the art to employ a "pass-transistor logic circuit" to reduce a number of elements and power consumption, and to improve operating speed.'
^ Shirriff, Ken (2013). "Reverse-engineering the Z-80: the silicon for two interesting gates explained".
^ Yeap, Gary K. (2012) [1998]. Practical Low Power Digital VLSI Design. Springer. p. 197. ISBN 978-1-4615-6065-4.
^ Oklobdzija, Vojin G. (19 December 2017). Digital Design and Fabrication. CRC Press. pp. 2–39. ISBN 9780849386046.
^ Yano, Kuniaki; Yamanaka, Toshiaki Yamanaka; Nishida, Takeshi; Saito, Mitsuo; Shimohigashi, Katsuhiro; Shimizu, Atsushi (1990). "A 3.8-ns CMOS 16x16-b multiplier using complementary pass-transistor logic". IEEE Journal of Solid-State Circuits. 25 (2): 388–395. Bibcode:1990IJSSC..25..388Y. doi:10.1109/4.52161.
^ Reynders, Nele; Dehaene, Wim (2015). Ultra-Low-Voltage Design of Energy-Efficient Digital Circuits. Analog Circuits And Signal Processing (ACSP). Springer Switzerland. doi:10.1007/978-3-319-16136-5. ISBN 978-3-319-16135-8. ISSN 1872-082X. LCCN 2015935431.
^ Chen, Wai-Kai, ed. (2003). Logic Design. CRC Press. pp. 15–7. ISBN 978-0-203-01015-0. OCLC 1029500642.
^ Oklobdzija, Vojin G., ed. (2001). The Computer Engineering Handbook. Taylor & Francis. pp. 2-23–2-24. ISBN 978-0-8493-0885-7.
^ Pal, Ajit (2014). "5.2.3 Pass-Transistor Logic Families". Low-Power VLSI Circuits and Systems. Springer. pp. 109–110. ISBN 978-81-322-1937-8.
^ Leondes, Cornelius T. (1995). Digital signal processing systems: implementation techniques. Elsevier. p. 2. ISBN 0-12-012768-7.