File:CMOS NOR gate with two inputs.svg
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Summary
| Description |
English: A NOR gate implemented in CMOS. The two n-type transistors on the bottom in parallel set the output Y to low (zero) when either A or B is high; the two p-type transistors in series at the top pull the output to high (one) if both inputs are zero. Because p-type transistors are slower than n-type transistors, a NOR gate is less efficient than a NAND gate in CMOS. |
| Date | |
| Source | Own work |
| Author | Trex4321 |
Created with the Digital logic simulator, https://github.com/hneemann/Digital
Licensing
I, the copyright holder of this work, hereby publish it under the following license:
 
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This file is made available under the Creative Commons CC0 1.0 Universal Public Domain Dedication. |
| The person who associated a work with this deed has dedicated the work to the public domain by waiving all of their rights to the work worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law. You can copy, modify, distribute and perform the work, even for commercial purposes, all without asking permission.
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 15:14, 6 December 2024 | | 241 × 247 (7 KB) | Trex4321 | Uploaded own work with UploadWizard |
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