In integrated circuit design, integrated circuit (IC) layout, also known IC mask layout or mask design, is the representation of an integrated circuit in terms of planar geometric shapes which correspond to the patterns of metal, oxide, or semiconductor layers that make up the components of the integrated circuit. Originally the overall process was called tapeout, as historically early ICs used graphical black crepe tape on mylar media for photo imaging (erroneously believed[who?] to reference magnetic data—the photo process greatly predated magnetic media[citation needed]).
When using a standard process—where the interaction of the many chemical, thermal, and photographic variables is known and carefully controlled—the behaviour of the final integrated circuit depends largely on the positions and interconnections of the geometric shapes. Using a computer-aided layout tool, the layout engineer—or layout technician—places and connects all of the components that make up the chip such that they meet certain criteria—typically: performance, size, density, and manufacturability. This practice is often subdivided between two primary layout disciplines: analog and digital.
The generated layout must pass a series of checks in a process known as physical verification. The most common checks in this verification process are[1][2]
- Design rule checking (DRC),
- Layout versus schematic (LVS),
- parasitic extraction,
- antenna rule checking, and
- electrical rule checking (ERC).
When all verification is complete, layout post processing[3] is applied where the data is also translated into an industry-standard format, typically GDSII, and sent to a semiconductor foundry. The milestone completion of the layout process of sending this data to the foundry is now colloquially called "tapeout". The foundry converts the data into mask data[3] and uses it to generate the photomasks used in a photolithographic process of semiconductor device fabrication.
In the earlier, simpler, days of IC design, layout was done by hand using opaque tapes and films, an evolution derived from early days of printed circuit board (PCB) design -- tape-out.
Modern IC layout is done with the aid of IC layout editor software, mostly automatically using EDA tools, including place and route tools or schematic-driven layout tools. Typically this involves a library of standard cells.
The manual operation of choosing and positioning the geometric shapes is informally known as "polygon pushing".[4][5][6][7][8]
See also
editReferences
edit- ^ A. Kahng, J. Lienig, I. Markov, J. Hu: VLSI Physical Design: From Graph Partitioning to Timing Closure, doi:10.1007/978-3-030-96415-3, ISBN 978-3-030-96414-6, p. 9.
- ^ Basu, Joydeep (2019-10-09). "From Design to Tape-out in SCL 180 nm CMOS Integrated Circuit Fabrication Technology". IETE Journal of Education. 60 (2): 51–64. arXiv:1908.10674. doi:10.1080/09747338.2019.1657787. S2CID 201657819.
- ^ a b J. Lienig, J. Scheible (2020). "Chap. 3.3: Mask Data: Layout Post Processing". Fundamentals of Layout Design for Electronic Circuits. Springer. p. 102-110. doi:10.1007/978-3-030-39284-0. ISBN 978-3-030-39284-0. S2CID 215840278.
- ^ Dirk Jansen, editor. "The Electronic Design Automation Handbook". 2010. p. 39.
- ^ Dan Clein. "CMOS IC Layout: Concepts, Methodologies, and Tools". 1999 p. 60.
- ^ "Conference Record". 1987. p. 118.
- ^ Charles A. Harper; Harold C. Jones. "Active Electronic Component Handbook". 1996. p. 2
- ^ Riko Radojcic. "Managing More-than-Moore Integration Technology Development". 2018. p. 99
Further reading
edit- Clein, D. (2000). CMOS IC Layout. Newnes. ISBN 0-7506-7194-7
- Hastings, A. (2005). The Art of Analog Layout. Prentice Hall. ISBN 0-13-146410-8
- Lienig, J., Scheible, J. (2020). Fundamentals of Layout Design for Electronic Circuits. Springer. doi:10.1007/978-3-030-39284-0. ISBN 978-3-030-39284-0. S2CID 215840278.
{{cite book}}: CS1 maint: multiple names: authors list (link) - Saint, Ch. and J. (2002). IC Layout Basics. McGraw-Hill. ISBN 0-07-138625-4