Unum (number format)

Unums (universal numbers) are a family of number formats and arithmetic for implementing real numbers on a computer, proposed by John L. Gustafson in 2015. They are designed as an alternative to the ubiquitous IEEE 754 floating-point standard. The latest version is known as posits.

Type I Unum

The first version of unums, formally known as Type I unum, was introduced in Gustafson's book The End of Error as a superset of the IEEE-754 floating-point format. The defining features of the Type I unum format are:

• a variable-width storage format for both the significand and exponent, and
• a u-bit, which determines whether the unum corresponds to an exact number (u = 0), or an interval between consecutive exact unums (u = 1). In this way, the unums cover the entire extended real number line [−∞,+∞].

For computation with the format, Gustafson proposed using interval arithmetic with a pair of unums, what he called a ubound, providing the guarantee that the resulting interval contains the exact solution.

William M. Kahan and Gustafson debated unums at the Arith23 conference.

Type II Unum

Type II Unums were introduced in 2016 as a redesign of Unums that broke IEEE-754 compatibility.

Posit (Type III Unum)

In February 2017, Gustafson officially introduced Type III unums (posits), for fixed floating-point-like values and valids for interval arithmetic. In March 2022, a standard was ratified and published by the Posit Working Group.

Posits are a hardware-friendly version of unum where difficulties faced in the original type I unum due to its variable size are resolved. Compared to IEEE 754 floats of similar size, posits offer a bigger dynamic range and more fraction bits for values with magnitude near 1 (but fewer fraction bits for very large or very small values), and Gustafson claims that they offer better accuracy. Studies confirm that for some applications, posits with quire out-perform floats in accuracy. Posits have superior accuracy in the range near one, where most computations occur. This makes it very attractive to the current trend in deep learning to minimize the number of bits used. It potentially helps any application to accelerate by enabling the use of fewer bits (since it has more fraction bits for accuracy) reducing network and memory bandwidth and power requirements.

The format of an n-bit posit is given a label of "posit" followed by the decimal digits of n (e.g., the 16-bit posit format is "posit16") and consists of four sequential fields:

1. sign: 1 bit, representing an unsigned integer s
2. regime: at least 2 bits and up to (n − 1), representing an unsigned integer r as described below
3. exponent: up to 2 bits as available after regime, representing an unsigned integer e
4. fraction: all remaining bits available after exponent, representing a non-negative real dyadic rational f less than 1

The regime field uses unary coding of k identical bits, followed by a bit of opposite value if any remaining bits are available, to represent an unsigned integer r that is −k if the first bit is 0 or k − 1 if the first bit is 1. The sign, exponent, and fraction fields are analogous to IEEE 754 sign, exponent, and significand fields (respectively), except that the posit exponent and fraction fields may be absent or truncated and implicitly extended with zeroes—an absent exponent is treated as 00₂ (representing 0), a one-bit exponent E₁ is treated as E10₂ (representing the integer 0 if E₁ is 0 or 2 if E₁ is 1), and an absent fraction is treated as 0.

The two encodings in which all non-sign bits are 0 have special interpretations:

• If the sign bit is 1, the posit value is NaR ("not a real")
• If the sign bit is 0, the posit value is 0 (which is unsigned and the only value for which the sign function returns 0)

Otherwise, the posit value is equal to ${\textstyle ((1-3s)+f)\times 2^{(1-2s)\times (4r+e+s)}}$, in which r scales by powers of 16, e scales by powers of 2, f distributes values uniformly between adjacent combinations of (r, e), and s adjusts the sign symmetrically about 0.

Examples

type (positn)	Binary	Value	Notes
Any	1 0…	NaR	anything not mathematically definable as a unique real number
Any	0 0…	0
Any	0 10…	1
Any	1 10…	−1
Any	0 01 11 0…	0.5
Any	0 0…1	${\textstyle 2^{-4n+8}}$	smallest positive value
Any	0 1…	${\textstyle 2^{4n-8}}$	largest positive value
posit8	0 0000001	${\textstyle 2^{-24}\approx 6.0\times 10^{-8}}$	smallest positive value
posit8	0 1111111	${\textstyle 2^{24}\approx 1.7\times 10^{7}}$	largest positive value
posit16	0 000000000000001	${\textstyle 2^{-56}\approx 1.4\times 10^{-17}}$	smallest positive value
posit16	0 111111111111111	${\textstyle 2^{56}\approx 7.2\times 10^{16}}$	largest positive value
posit32	0 0000000000000000000000000000001	${\textstyle 2^{-120}\approx 7.5\times 10^{-37}}$	smallest positive value
posit32	0 1111111111111111111111111111111	${\textstyle 2^{120}\approx 1.3\times 10^{36}}$	largest positive value

Note: 32-bit posit is expected to be sufficient to solve almost all classes of applications.

Quire

For each positn type of precision ${\textstyle n}$, the standard defines a corresponding "quire" type quiren of precision ${\textstyle 16\times n}$, used to accumulate exact sums of products of those posits without rounding or overflow in dot products for vectors of up to 2³¹ or more elements (the exact limit is $2^{23+4n}$). The quire format is a two's complement signed integer, interpreted as a multiple of units of magnitude $2^{16-8n}$ except for the special value with a leading sign bit of 1 and all other bits equal to 0 (which represents NaR). Quires are based on the work of Ulrich W. Kulisch and Willard L. Miranker.

Valid

Valids are described as a Type III Unum mode that bounds results in a given range.

Implementations

Several software and hardware solutions implement posits. The first complete parameterized posit arithmetic hardware generator was proposed in 2018.

Unum implementations have been explored in Julia and MATLAB. A C++ version with support for any posit sizes combined with any number of exponent bits is available. A fast implementation in C, SoftPosit, provided by the NGA research team based on Berkeley SoftFloat adds to the available software implementations.

Project author	Type	Precisions	Quire Support?	Speed	Testing	Notes
GP-GPU VividSparks	World's first FPGA GPGPU	32	Yes	~3.2 TPOPS	Exhaustive. No known bugs.	RacEr GP-GPU has 512 cores
SoftPosit A*STAR	C library based on Berkeley SoftFloat C++ wrapper to override operators Python wrapper using SWIG of SoftPosit	8, 16, 32 published and complete;	Yes	~60 to 110 MPOPS on x86 core (Broadwell)	8: Exhaustive; 16: Exhaustive except FMA, quire 32: Exhaustive test is still in progress. No known bugs.	Open source license. Fastest and most comprehensive C library for posits presently. Designed for plug-in comparison of IEEE floats and posits.
posit4.nb A*STAR	Mathematica notebook	All	Yes	< 80 KPOPS	Exhaustive for low precisions. No known bugs.	Open source (MIT license). Original definition and prototype. Most complete environment for comparing IEEE floats and posits. Many examples of use, including linear solvers
posit-javascript A*STAR	JavaScript widget	Convert decimal to posit 6, 8, 16, 32; generate tables 2–17 with es 1–4.	N/A	N/A; interactive widget	Fully tested	Table generator and conversion
Universal Stillwater Supercomputing, Inc	C++ template library C library Python wrapper Golang library	Arbitrary precision posit float valid (p) Unum type 1 (p) Unum type 2 (p)	Arbitrary quire configurations with programmable capacity	posit<4,0> 1 GPOPS posit<8,0> 130 MPOPS posit<16,1> 115 MPOPS posit<32,2> 105 MPOPS posit<64,3> 50 MPOPS posit<128,4> 1 MPOPS posit<256,5> 800 KPOPS	Complete validation suite for arbitrary posits Randoms for large posit configs. Uses induction to prove nbits+1 is correct no known bugs	Open source. MIT license. Fully integrated with C/C++ types and automatic conversions. Supports full C++ math library (native and conversion to/from IEEE). Runtime integrations: MTL4/MTL5, Eigen, Trilinos, HPR-BLAS. Application integrations: G+SMO, FDBB, FEniCS, ODEintV2, TVM.ai. Hardware accelerator integration (Xilinx, Intel, Achronix).
Speedgo Chung Shin Yee	Python library	All	No	~20 MPOPS	Extensive; no known bugs	Open source (MIT license)
softposit-rkt David Thien	SoftPosit bindings for Racket	All	Yes	Un­known	Un­known
sfpy Bill Zorn	SoftPosit bindings for Python	All	Yes	~20–45 MPOPS on 4.9 GHz Skylake core	Un­known
positsoctave Diego Coelho	Octave implementation	All	No	Un­known	Limited Testing; no known bugs	GNU GPL
Sigmoid Numbers Isaac Yonemoto	Julia library	All <32, all ES	Yes	Un­known	No known bugs (posits). Division bugs (valids)	Leverages Julia's templated mathematics standard library, can natively do matrix and tensor operations, complex numbers, FFT, DiffEQ. Support for valids
FastSigmoid Isaac Yonemoto	Julia and C/C++ library	8, 16, 32, all ES	No	Un­known	Known bug in 32-bit multiplication	Used by LLNL in shock studies
SoftPosit.jl Milan Klöwer	Julia library	Based on softposit; 8-bit (es=0..2) 16-bit (es=0..2) 24-bit (es=1..2) 32-bit (es=2)	Yes	Similar to A*STAR "SoftPosit" (Cerlane Leong)	Yes: Posit (8,0), Posit (16,1), Posit (32,2) Other formats lack full functionality	Open source. Issues and suggestions on GitHub. This project was developed due to the fact that SigmoidNumbers and FastSigmoid by Isaac Yonemoto is not maintained currently. Supports basic linear algebra functions in Julia (Matrix multiplication, Matrix solve, Elgen decomposition, etc.)
PySigmoid Ken Mercado	Python library	All	Yes	< 20 MPOPS	Un­known	Open source (MIT license). Easy-to-use interface. Neural net example. Comprehensive functions support.
cppPosit Federico Rossi, Emanuele Ruffaldi	C++ library	4 to 64 (any es value); "Template version is 2 to 63 bits"	No	Un­known	A few basic tests	4 levels of operations working with posits. Special support for NaN types (non-standard)
bfp:Beyond Floating Point Clément Guérin	C++ library	Any	No	Un­known	Bugs found; status of fixes unknown	Supports + – × ÷ √ reciprocal, negate, compare
Verilog.jl Isaac Yonemoto	Julia and Verilog	8, 16, 32, ES=0	No	Un­known	Comprehensively tested for 8-bit, no known bugs	Intended for Deep Learning applications Addition, Subtraction and Multiplication only. A proof of concept matrix multiplier has been built, but is off-spec in its precision
Lombiq Arithmetics Lombiq Technologies	C# with Hastlayer for hardware generation	8, 16, 32. (64bits in progress)	Yes	10 MPOPS Click here for more	Partial	Requires Microsoft .Net APIs
DeepfloatJeff Johnson, Facebook	SystemVerilog	Any (parameterized SystemVerilog)	Yes	N/A (RTL for FPGA/ASIC designs)	Limited	Does not strictly conform to posit spec. Supports +,-,/,*. Implements both logarithmic posit and normal, "linear" posits License: CC-BY-NC 4.0 at present
Tokyo Tech	FPGA	16, 32, extendable	No	"2 GHz", not translated to MPOPS	Partial; known rounding bugs	Yet to be open-source
PACoGen: Posit Arthmetic Core GeneratorManish Kumar Jaiswal	Verilog HDL for Posit Arithmetic	Any precision. Able to generate any combination of word-size (N) and exponent-size (ES)	No	Speed of design is based on the underlying hardware platform (ASIC/FPGA)	Exhaustive tests for 8-bit posit. Multi-million random tests are performed for up to 32-bit posit with various ES combinations	It supports rounding-to-nearest rounding method.
Vinay Saxena, Research and Technology Centre, Robert Bosch, India (RTC-IN) and Farhad Merchant, RWTH Aachen University	Verilog generator for VLSI, FPGA	All	No	Similar to floats of same bit size	N=8 - ES=2 | N=7,8,9,10,11,12 Selective (20000*65536) combinations for - ES=1 | N=16	To be used in commercial products. To the best of our knowledge. ***First ever integration of posits in RISC-V***
Posit-enabled RISC-V core (Sugandha Tiwari, Neel Gala, Chester Rebeiro, V.Kamakoti, IIT MADRAS)	BSV (Bluespec System Verilog) Implementation	32-bit posit with (es=2) and (es=3)	No	—	Verified against SoftPosit for (es=2) and tested with several applications for (es=2) and (es=3). No known bugs.	First complete posit-capable RISC-V core. Supports dynamic switching between (es=2) and (es=3). More info here.
PERCIVAL David Mallasén	Open-Source Posit RISC-V Core with Quire Capability	Posit<32,2> with 512-bit quire	Yes	Speed of design is based on the underlying hardware platform (ASIC/FPGA)	Functionality testing of each posit instruction.	Application-level posit-capable RISC-V core based on CVA6 that can execute all posit instructions, including the quire fused operations. PERCIVAL is the first work that integrates the complete posit ISA and quire in hardware. It allows the native execution of posit instructions as well as the standard floating-point ones simultaneously.
LibPosit Chris Lomont	Single file C# MIT Licensed	Any size	No		Extensive; no known bugs	Ops: arithmetic, comparisons, sqrt, sin, cos, tan, acos, asin, atan, pow, exp, log
unumjl REX Computing	FPGA version of the "Neo" VLIW processor with posit numeric unit	32	No	~1.2 GPOPS	Extensive; no known bugs	No divide or square root. First full processor design to replace floats with posits.
PNU: Posit Numeric Unit Calligo Tech	World's first posit-enabled ASIC with octa-core RISC-V processor and Quire implemented. PCIe accelerator card with this silicon will be ready June 2024 Fully software stack with compilers, debugger, IDE environment and math libraries for applications. C, C++, Python languages supported Applications tested successfully - image and video compression, more to come	<32, 2> with Quire 512 bits support. <64, 3>	Yes - Fully supported.	500 MHz * 8 Cores	Exhaustive tests completed for 32 bits and 64 bits with Quire support completed. Applications tested and being made available for seamless adoption www.calligotech.com	Fully integrated with C/C++ types and automatic conversions. Supports full C++ math library (native and conversion to/from IEEE). Runtime integrations: GNU Utils, OpenBLAS, CBLAS. Application integrations: in progress. Compiler support extended: C/C++, G++, GFortran & LLVM (in progress).
IBM-TACC Jianyu Chen	Specific-purpose FPGA	32	Yes	16–64 GPOPS	Only one known case tested	Does 128-by-128 matrix-matrix multiplication (SGEMM) using quire.
Deep PeNSieve Raul Murillo	Python library (software)	8, 16, 32	Yes	Un­known	Un­known	A DNN framework using posits
Gosit Jaap Aarts	Pure Go library	16/1 32/2 (included is a generic 32/ES for ES<32)	No	80 MPOPS for div32/2 and similar linear functions. Much higher for truncate and much lower for exp.	Fuzzing against C softposit with a lot of iterations for 16/1 and 32/2. Explicitly testing edge cases found.	(MIT license) The implementations where ES is constant the code is generated. The generator should be able to generate for all sizes {8,16,32} and ES below the size. However, the ones not included into the library by default are not tested, fuzzed, or supported. For some operations on 32/ES, mixing and matching ES is possible. However, this is not tested.

SoftPosit

SoftPosit is a software implementation of posits based on Berkeley SoftFloat. It allows software comparison between posits and floats. It currently supports

• Add
• Subtract
• Multiply
• Divide
• Fused-multiply-add
• Fused-dot-product (with quire)
• Square root
• Convert posit to signed and unsigned integer
• Convert signed and unsigned integer to posit
• Convert posit to another posit size
• Less than, equal, less than equal comparison
• Round to nearest integer

Helper functions

• convert double to posit
• convert posit to double
• cast unsigned integer to posit

It works for 16-bit posits with one exponent bit and 8-bit posit with zero exponent bit. Support for 32-bit posits and flexible type (2-32 bits with two exponent bits) is pending validation. It supports x86_64 systems. It has been tested on GNU gcc (SUSE Linux) 4.8.5 Apple LLVM version 9.1.0 (clang-902.0.39.2).

Examples

Add with posit8_t

#include "softposit.h"

int main(int argc, char *argv[]) {
    posit8_t pA, pB, pZ;
    pA = castP8(0xF2);
    pB = castP8(0x23);
    pZ = p8_add(pA, pB);

    // To check answer by converting it to double
    double dZ = convertP8ToDouble(pZ);
    printf("dZ: %.15f\n", dZ);

    // To print result in binary (warning: non-portable code)
    uint8_t uiZ = castUI8(pZ);
    printBinary((uint64_t*)&uiZ, 8);

    return 0;
}

Fused dot product with quire16_t

// Convert double to posit
posit16_t pA = convertDoubleToP16(1.02783203125);
posit16_t pB = convertDoubleToP16(0.987060546875);
posit16_t pC = convertDoubleToP16(0.4998779296875);
posit16_t pD = convertDoubleToP16(0.8797607421875);

quire16_t qZ;

// Set quire to 0
qZ = q16_clr(qZ);

// Accumulate products without roundings
qZ = q16_fdp_add(qZ, pA, pB);
qZ = q16_fdp_add(qZ, pC, pD);

// Convert back to posit
posit16_t pZ = q16_to_p16(qZ);

// To check answer
double dZ = convertP16ToDouble(pZ);

Critique

William M. Kahan, the principal architect of IEEE 754-1985 criticizes type I unums on the following grounds (some are addressed in type II and type III standards):

• The description of unums sidesteps using calculus for solving physics problems.
• Unums can be expensive in terms of time and power consumption.
• Each computation in unum space is likely to change the bit length of the structure. This requires either unpacking them into a fixed-size space, or data allocation, deallocation, and garbage collection during unum operations, similar to the issues for dealing with variable-length records in mass storage.
• Unums provide only two kinds of numerical exception, quiet and signaling NaN (Not-a-Number).
• Unum computation may deliver overly loose bounds from the selection of an algebraically correct but numerically unstable algorithm.
• The benefits of unum over short precision floating point for problems requiring low precision are not obvious.
• Solving differential equations and evaluating integrals with unums guarantee correct answers but may not be as fast as methods that usually work.

See also

• Karlsruhe Accurate Arithmetic (KAA)
• Q (number format)
• Significant figures
• Floating-point error mitigation
• Elias gamma (γ) code
• Tapered floating point (TFP)

Further reading

• Gustafson, John L. (March 2013). "Right-Sizing Precision: Unleashed Computing: The need to right-size precision to save energy, bandwidth, storage, and electrical power" (PDF). Archived (PDF) from the original on 2016-06-06. Retrieved 2016-06-06.
• Brueckner, Rich (2015-03-02). "Slidecast: John Gustafson Explains Energy Efficient Unum Computing". The Rich Report. Inside HPC. Archived from the original on 2016-07-10. Retrieved 2016-06-10.
• Gustafson, John L. (2015). "The end of numerical error" (PDF). Archived (PDF) from the original on 2016-06-06. Retrieved 2016-06-06.
• Gustafson, John L. (2016-06-03) [2016-02-22]. "A Radical Approach to Computation with Real Numbers – Unums version 2.0" (PPT). Archived from the original on 2016-07-10. Retrieved 2016-07-10. (NB. PDFs come without notes: [5] [6])
• Gustafson, John L. (2016-06-06). "An Energy-Efficient and massively parallel approach to valid numerics" (PPT). OCRAR Seminar. Archived from the original on 2016-07-10. Retrieved 2016-07-10. [7] [8]
• Gustafson, John L. (2016). "A Radical Approach to Computation with Real Numbers" (PDF). SuperFri.org. Archived (PDF) from the original on 2016-07-10. Retrieved 2016-07-10.
• Kulisch, Ulrich W. (2015). "Up-to-date Interval Arithmetic from closed intervals to connected sets of real numbers" (PDF) (preprint). Institut für Angewandte und Numerische Mathematik – Karlsruhe Institute of Technology (KIT), Germany. ID 15/02. Archived (PDF) from the original on 2016-07-12. Retrieved 2016-07-12.
• Risse, Thomas (2016-03-10). "Unum – an expedient extension of IEEE 754" (PDF) (presentation). London South Bank University (LSBU), UK: Institute of Informatics & Automation (IIA), Faculty EEE & CS, Bremen University of Applied Sciences, Germany. Archived (PDF) from the original on 2016-07-12. Retrieved 2016-07-12.
• Kahan, William M. (2016-07-15). "Prof. W. Kahan's Comments on SORN Arithmetic" (PDF). Archived (PDF) from the original on 2016-08-01. Retrieved 2016-08-01.
• Hunhold, Laslo (2016-11-08). The Unum Number Format: Mathematical Foundations, Implementation and Comparison to IEEE 754 Floating-Point Numbers (PDF) (Bachelor thesis). Universität zu Köln, Mathematisches Institut. arXiv:1701.00722v1. Archived (PDF) from the original on 2017-01-07. Retrieved 2016-10-23.
• Sterbenz, Pat H. (1974-05-01). Floating-Point Computation. Prentice-Hall Series in Automatic Computation (1st ed.). Englewood Cliffs, New Jersey, USA: Prentice Hall. ISBN 0-13-322495-3.
• Cave, Skip (2016-08-17). "J Programming Language Implementation of 3-bit, 4-bit, 8-bit and 16-bit Precision Unums". Retrieved 2017-05-03. (Roger Stokes' download link: [9])
• Ingole, Deepak (2017-09-28). Embedded Implementation of Explicit Model Predictive Control (PhD Thesis). Slovak University of Technology in Bratislava, Slovakia.

External links

• "Conference for Next Generation Arithmetic (CoNGA)". 2017. Archived from the original on 2017-11-04. Retrieved 2017-11-04.
• "SoftPosit". 2018. Retrieved 2018-06-13.
• "Community Source Code Contribution". 2018. Retrieved 2018-06-13.
• "Anatomy of a posit number". 2018-04-11. Retrieved 2019-08-09.