Attention for the earth's AHDL or FIR filter developers. I'm one of developers to interest developing FIR filter using CPLD or FPGA. The FIR filter created by us is another new thing. In general speaking, the minimization of logic function is performed by the traditional methods. But we found new method to minimize the boolean function by the decimal method. If you should like to know the new minimization method, you may send a mail to yongzhi_1977@163.com. You may challenge our team to develop the FIR filter or the other digital circuit to using CPLD or FPGA. OK! Goodbye!!! I'm waiting for your challenges!!! In specially, if you are the team like the ALTERA corporation, I'm very happy.
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