Duncan's taxonomy is a classification of computer architectures, proposed by Ralph Duncan in 1990.[1] Duncan suggested modifications to Flynn's taxonomy[2] to include pipelined vector processes.[3]
Taxonomy
editThe taxonomy was developed during 1988-1990 and was first published in 1990. Its original categories are indicated below.
Synchronous architectures
editThis category includes all the parallel architectures that coordinate concurrent execution in lockstep fashion and do so via mechanisms such as global clocks, central control units or vector unit controllers. Further subdivision of this category is made primarily on the basis of the synchronization mechanism.[1]
Pipelined vector processors
editPipelined vector processors are characterized by pipelined functional units that accept a sequential stream of array or vector elements, such that different stages in a filled pipeline are processing different elements of the vector at a given time.[4] Parallelism is provided both by the pipelining in individual functional units described above, as well as by operating multiple units of this kind in parallel and by chaining the output of one unit into another unit as input.[4]
Vector architectures that stream vector elements into functional units from special vector registers are termed register-to-register architectures, while those that feed functional units from special memory buffers are designated as memory-to-memory architectures.[1] Early examples of register-to-register architectures from the 1960s and early 1970s include the Cray-1[5] and Fujitsu VP-200, while the Control Data Corporation STAR-100, CDC 205 and the Texas Instruments Advanced Scientific Computer are early examples of memory-to-memory vector architectures.[6]
The late 1980s and early 1990s saw the introduction of vector architectures, such as the Cray Y-MP/4 and Nippon Electric Corporation SX-3 that supported 4-10 vector processors with a shared memory (see NEC SX architecture). RISC-V RVV may mark the beginning of the modern revival of Vector processing.[speculation?]
SIMD
editThis scheme uses the SIMD (single instruction stream, multiple data stream) category from Flynn's taxonomy as a root class for processor array and associative memory subclasses. SIMD architectures[7] are characterized by having a control unit broadcast a common instruction to all processing elements, which execute that instruction in lockstep on diverse operands from local data. Common features include the ability for individual processors to disable an instruction and the ability to propagate instruction results to immediate neighbors over an interconnection network.
Processor array
editAssociative memory
editSystolic array
editSystolic arrays, proposed during the 1980s,[8] are multiprocessors in which data and partial results are rhythmically pumped from processor to processor through a regular, local interconnection network.[1] Systolic architectures use a global clock and explicit timing delays to synchronize data flow from processor to processor.[1] Each processor in a systolic system executes an invariant sequence of instructions before data and results are pulsed to neighboring processors.[8]
MIMD architectures
editBased on Flynn's multiple-instruction-multiple-data streams terminology, this category spans a wide spectrum of architectures in which processors execute multiple instruction sequences on (potentially) dissimilar data streams without strict synchronization. Although both instruction and data streams can be different for each processor, they need not be. Thus, MIMD architectures can run identical programs that are in various stages at any given time, run unique instruction and data streams on each processor or execute a combination of each these scenarios. This category is subdivided further primarily on the basis of memory organization.[1]
Distributed memory
editShared memory
editMIMD-paradigm architectures
editThe MIMD-based paradigms category subsumes systems in which a specific programming or execution paradigm is at least as fundamental to the architectural design as structural considerations are. Thus, the design of dataflow architectures and reduction machines is as much the product of supporting their distinctive execution paradigm as it is a product of connecting processors and memories in MIMD fashion. The category's subdivisions are defined by these paradigms.[1]
MIMD/SIMD hybrid
editDataflow machine
editReduction machine
editWavefront array
editReferences
edit- ^ a b c d e f g Duncan, Ralph, "A Survey of Parallel Computer Architectures", IEEE Computer. February 1990, pp. 5-16.
- ^ Flynn, M.J., "Very High Speed Computing Systems", Proc. IEEE. Vol. 54, 1966, pp.1901-1909.
- ^ Introduction to Parallel Algorithms
- ^ a b Hwang, K., ed., Tutorial Supercomputers: Design and Applications. Computer Society Press, Los Alamitos, California, 1984, esp. chapters 1 and 2.
- ^ Russell, R.M., "The CRAY-1 Computer System," Comm. ACM, Jan. 1978, pp. 63-72.
- ^ Watson, W.J., The ASC: a Highly Modular Flexible Super Computer Architecture, Proc. AFIPS Fall Joint Computer Conference, 1972, pp. 221-228.
- ^ Michael Jurczyk and Thomas Schwederski,"SIMD-Processing: Concepts and Systems", pp. 649-679 in Parallel and Distributed Computing Handbook, A. Zomaya, ed., McGraw-Hill, 1996.
- ^ a b Kung, H.T., "Why Systolic Arrays?", Computer, Vol. 15, No. 1, Jan. 1982, pp. 37-46.
- C Xavier and S S Iyengar, Introduction to Parallel Programming