High-threshold logic

High-threshold logic (HTL), also known as low-speed logic (LSL) or high-level logic (HLL), is a variant of diode–transistor logic used in environments where noise is very high.

Schematic of basic unbuffered three-input HTL NAND gate

FZH251, four two-input HTL AND

Operation

The threshold values at the input to a logic gate determine whether a particular input is interpreted as a logic 0 or a logic 1 (e.g. anything less than 1 V is a logic 0, and anything above 3 V is a logic 1; in this example, the threshold values are 1 V and 3 V). HTL incorporates Zener diodes to create a large offset between logic 1 and logic 0 voltage levels. These devices usually ran off a 15 V power supply and were found in industrial control, where the high differential was intended to minimize the effect of noise.

Schematic of a real buffered two-input HTL NAND gate FZH101A; PV = 180 mW; tpd = 175 ns.

Advantages

• Increased noise margin
• High noise threshold value

Disadvantage

• Slow speed due to increased supply voltage resulting in use of high value resistors.
• High power drawn

Usage

It is used extensively in industrial environments. e.g.

• Logic controllers with heavy noise
• Heavy-process machinery

Similar circuits

The buffer in this device is exactly the same of what was used in RGB video output stages in TV circuits in the way that the upper NPN transistor quickly rises a cathode capacitance with a relatively high load resistor on the lower NPN transistor, while the lower NPN transistor controls the turning on of the output voltage.

The principle of improving charge–discharge parasitic capacitances used here is the same as in high-threshold logic circuits.

See also

• Diode logic (DL)
• Diode-transistor logic (DTL)
• Emitter-coupled logic (ECL)
• Integrated injection logic (I2L)
• Resistor–transistor logic (RTL)
• Transistor–transistor logic (TTL)