Thyristor RAM (T-RAM) is a type of random-access memory dating from 2009 invented and developed by T-RAM Semiconductor, which departs from the usual designs of memory cells, combining the strengths of the DRAM and SRAM: high density and high speed.[citation needed] This technology, which exploits the electrical property known as negative differential resistance and is called thin capacitively-coupled thyristor,[1] is used to create memory cells capable of very high packing densities. Due to this, the memory is highly scalable, and already has a storage density that is several times higher than found in conventional 6T SRAM. It was expected that the next generation of T-RAM memory will have the same density as DRAM.[by whom?]
This technology exploits the electrical property known as negative differential resistor and is characterized by the way in which its memory cells are built, combining DRAM efficiency in terms of space with that of SRAM in terms of speed. Very similar to the current 6T-SRAM, or SRAM memories with 6 cell transistors, is substantially different because the SRAM latch CMOS, consisting of 4 of the 6 transistors of each cell, is replaced by a bipolar latch PNP -NPN of a single Thyristor. The result is to significantly reduce the area occupied by each cell, thus obtaining a highly scalable memory that has already reached storage density several times higher than the current SRAM.
The Thyristor-RAM provides the best density / performance ratio available between the various integrated memories, matching the performance of an SRAM memory, but allowing 2-3 times greater storage density and lower power consumption. It is expected that the new generation of T-RAM memory will have the same storage density as DRAMs.
Related items
editReferences
edit- ^ "T - R a M". Archived from the original on 2009-05-23. Retrieved 2009-09-19. Description of the technology
External links
edit- T-RAM Semiconductor
- T-RAM Description
- Farid Nemati (T-RAM Semiconductor), Thyristor RAM (T-RAM): A High-Speed High-Density Embedded Memory. Technology for Nano-scale CMOS / 2007 Hot Chips Conference, August 21, 2007
- EE Times: GlobalFoundries to apply thyristor-RAM at 32-nm node
- Semiconductor International: GlobalFoundries Outlines 22 nm Roadmap[permanent dead link]
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