In computer science, a tagged architecture is a type of computer architecture where every word of memory constitutes a tagged union, being divided into a number of bits of data, and a tag section that describes the type of the data: how it is to be interpreted, and, if it is a reference, the type of the object that it points to.[1][2][3]
Precursors
editSome early systems use tagging of data in memory but do not have all of the characteristics now consider to be part of tagged architectures.
RCA 601
editThe RCA 601[4] has a 3-bit tag register and a 3-bit tag for every 24-bit half-word. Every instruction can request a test for equal or unequal tag, and cause a maskable interrupt if the specified match fails. There is no architectural connection between the tag and the contents of the half-word; it is strictly determined by the software.
Burroughs B5000, B5500 and B5700
editThe Burroughs B5000[5], B5500[6] and B5700 have 48-bit words with no appended tag field. However, while there are no tag fields for character, instruction or numeric (floating point) words, all of the control word formats include a 3-bit tag. However, the replacement architecture, starting with the B6500, does have a tag for every word.
Architecture
editIn contrast, program and data memory are indistinguishable in the von Neumann architecture, making the way the memory is referenced critical to interpret the correct meaning.
Notable examples of American tagged architectures were the Lisp machines, which had tagged pointer support at the hardware and opcode level, the Burroughs B6500 and successors, which have a data-driven tagged and descriptor-based architecture, and the non-commercial Rice Computer.[7] Both the Burroughs and Lisp machine are examples of high-level language computer architectures, where the tagging is used to support types from a high-level language at the hardware level.
In addition to this, the original Xerox Smalltalk implementation used the least-significant bit of each 16-bit word as a tag bit: if it was clear then the hardware would accept it as an aligned memory address while if it was set it was treated as a (shifted) 15-bit integer. Current Intel documentation mentions that the lower bits of a memory address might be similarly used by some interpreter-based systems.
In the Soviet Union, the Elbrus series of supercomputers pioneered the use of tagged architectures in 1973.
See also
editReferences
edit- ^ The Memory Management Glossary: Tagged architecture
- ^ Feustel, Edward A. (July 1973). "On the Advantages of Tagged Architecture" (PDF). IEEE Transactions on Computers: 644–656. Archived (PDF) from the original on May 23, 2013. Retrieved January 21, 2013.
- ^ Feustel, Edward A. (1972). "The Rice Research Computer -- A tagged architecture" (PDF). Proceedings of the 1972 Spring Joint Computer Conference. American Federation of Information Processing Societies (AFIPS). pp. 369–377. Archived (PDF) from the original on September 24, 2015. Retrieved July 27, 2014.
- ^ "Tags". RCA 601 - Electronic Data Processing System - General Information Manual. RCA. March 1961. pp. 26–27. 96-15-000.
- ^ Burroughs (1963), The Operational Characteristics of the Processors for the Burroughs B5000 (PDF), Revision A, 5000-21005
- ^ Burroughs (May 1967), Burroughs B5500 Information Processing System Reference Manual (PDF), 1021326
- ^ Thornton, Adam. "A Brief History of the Rice Computer 1959-1971". Archived from the original on February 24, 2008. Retrieved January 31, 2013. (mostly written in [or before] 1994, and archived by the Wayback Machine on a date indicated [by "20080224"] in the URL)