Talk:Comparison of Nvidia nForce chipsets
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A note should be issued warning the change of PCIE 1.0 to PCIE 2.0 from nForce 700 series onwards. [1]
Geforce 6100 / 6150 + nForce 410 / 430
editShouldn't the nForce 4 based Geforce 6100/6150 types with their 410/430 southbridges be included in this list? —Preceding unsigned comment added by 80.61.226.121 (talk) 19:11, 18 August 2010 (UTC)
duplicate?
editIsn't this a duplicate of List of Nvidia graphics processing units? 2A02:8420:508D:CC00:56E6:FCFF:FEDB:2BBA (talk) 22:03, 29 March 2015 (UTC)
nForce 790i Ultra SLI missing
editI think this should be in the table, I can find a lot of references to it online. It seems to be nearly identical to the nForce 790i SLI except that it has support for 2000MHz DDR3.
I'm not sure what the release date or codename are though; they might be the same as the 790i SLI.
Here's some sources
- https://www.nvidia.com/docs/IO/52333/NVIDIA_EPP2_TB.pdf
- https://www.nvidia.com/docs/IO/52280/LC_NV_motherboards_INTEL_Mar08_web.pdf
- https://www.nvidia.com/object/product_nforce_790i_ultra_sli_us.html
- https://www.pcper.com/reviews/Motherboards/EVGA-nForce-790i-Ultra-SLI-Motherboard-and-Chipset-Review?aid=536&type=expert&pid=12
- https://hothardware.com/reviews/nvidia-nforce-790i-sli-ultra-and-geforce-9800-gx2
End of production for nForce (additional context)
editNot mentioned in the article (and it would be original research to include without further references):
Rambus filed at least two tariff / patent complaints with the USITC. It appears starting in 2010 a whole swath of chips containing certain types of RAM controllers was to be blocked from import from the United States. This may partially explain why the AMDʰ-compatible versions were also discontinued.
References:
- USITC Investigation No. 337-TA-661: Initial Determination
- USITC Investigation No. 337-TA-753: summary
- US Patent 6,470,405; Protocol for communication with dynamic memory
- US Patent 6,591,353; Protocol for communication with dynamic memory
- US Patent 7,287,109; Method of controlling a memory device having a memory core
- US Patent 7,177,998; Method, system and memory controller utilizing adjustable read data delay settings
- US Patent 7,210,016; Method, system and memory controller utilizing adjustable write data delay settings