Talk:Delay-locked loop
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Suggested expansion of article
editThe addition of links to the following 2 articles may prove helpful:
Clock Management with PLLs and DLLs
Simulation and Modelling of Digital Delay-Locked Loops
(Sorry - I don't know how and am a bit busy to find out at present and am still looking for more information on how the variable delay line is usually implemented)
Accuracy question
editThe article suggests Dr. Combes is the innovator responsible for DLLs, yet below the references section patents are listed that issued more than 10 years before Dr. Combes articles.
This is problematic.
Drawings
editThe system figure is quite messy and unconventional. A smaller one is in german. Not a lot of citations. — Preceding unsigned comment added by 84.215.211.118 (talk) 21:53, 4 March 2013 (UTC)
I agree, the drawing is terrible. At first I thought it is some rendering error in my browser. 109.90.114.36 (talk) 15:38, 17 May 2016 (UTC)
Focus on DLL
editThe article is almost entirely a comparison with PLLs. But if you don't know how a PLL works, then that doesn't help at all trying to understand a DLL. It would be better to just describe DLLs by themselves. — Preceding unsigned comment added by 108.234.224.230 (talk) 07:35, 14 February 2020 (UTC)
Analog vs. Digital
editA true digital system is both clocked and discrete. Being unclocked by its data, I have rewritten this topic's entry paragraph to read pseudo-digital. July 2022. -- analog electronics engineer. Feel free to delete if uncontested.Barefootwhistler (talk) 03:22, 18 July 2022 (UTC)
No explanation of "order" and "type"
editThe article makes frequent use of the terms "order" and "type", but doesn't provide a good reference to the specific jargon/context that they are taken from. The best attempt is the mention of "the Control Systems jargon". This makes sentences such as "The loop order and type are both incremented by one" rather meaningless. --2A02:908:1065:960:0:0:0:1 (talk) 11:24, 7 October 2022 (UTC)