Talk:Hardware performance counter

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table with available counters

Latest comment: 12 years ago1 comment1 person in discussion

number of available hardware counter

Is this table of number of PMU events (like INS_RETIRED, Branch_mispredict, Cache_miss), or number of independent PMU channels (how much different events may be monitored at same moment).

18 for P4 looks for me too low in first case and too high in second case. `a5b (talk) 14:50, 11 August 2012 (UTC)Reply

Processor-specific?

Latest comment: 11 years ago1 comment1 person in discussion

This article only seems to discuss processors from the x86 family, but that is not stated.

CPU's have had some form of hardware counters for a long time, albeit not in the more refined forms now available. Even the 8-bit Zilog Z80 had an instruction memory access counter ("M1") which could be sampled to get an indication of program performance. — Preceding unsigned comment added by 27.252.177.16 (talk) 03:31, 21 August 2013 (UTC)Reply

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