Talk:IBM z10
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Processor Caches
editSomeone please sort out the L1 vs L1.5 vs L2 cache mess we seem to be in with this article. I'm more worried about the sizes of the caches. Martin Packer (talk) 00:56, 22 June 2008 (UTC)
- I just scanned through Charles Webb's presentation on the z6/z10 processor (see reference 2 in the article). He describes three caches: I-Cache of 64KB, D-Cache of 128KB, and 2nd-level and 3rd-level (24MB SRAM) caches. Again, that was just a quick scan. Tomorrow afternoon I hope to sit down and spend more time researching for this and other articles. --TreyGeek (talk) 04:48, 22 June 2008 (UTC)
- There are three levels of cache as TreyGeek noticed. I don't think the introduction of the term "L 1.5 cache" would satisfy anyone but the amrketing folks at IBM. I can't find any reason for this labeling. There are three levels, 1, 2 and 3. So MartinPacker's edit is wrong. The 24 MB off die cache is of the third level and is shared by all cores on an MCM, hence L3 cache. The L2 cache is 3 MB, is on-die and is private for the specific core. -- Henriok (talk) 13:17, 22 June 2008 (UTC)
- All I can tell you is that the announcement foils talk of levels 1, 1.5 and 2. Now whether this is in fact a deviation from standard nomenclature or not I can't say. What I can say is that 1 and 1.5 are one per processor and that 2 is per book. My hesitation on an extensive rework was that I'm not sure what the actual cache sizes are. I note the mention of Charles Webb's name. His foils came out about a year before the z10 machines (and the processors this article is about) were announced and shipped. Terminology may have changed. Actually I don't much mind about the nomenclature. But if I can find something definitive - which one can't call Charles' pitch - I'll try to reference it. Martin Packer (talk) 13:32, 22 June 2008 (UTC)
- I think it's clear that IBM uses the 1, 1.5 and 2 moniker for what the rest of the world uses 1, 2 and 3 for. The current Red Books on z10 uses this naming scheme.[1] I can only speculate why IBM does this, but it's probably a way to indicate that "L1.5" faster than usual "L2". But as cache hierarchies go, I can't find any technical difference. If we were to use IBM's way of naming things, we'll have to dedicate a portion in this article to sort things out. -- Henriok (talk) 14:12, 22 June 2008 (UTC)
- I think the "Level 1.5" name came about because it's also a 1-per-processor cache, just like the Level 1 cache. What we call "Level 2" is per book, with links to the caches in other books. By the way in z10 we have links to ALL the other books, so we don't have the z990 / z9 phenomenon of some L2 caches being only accessible by TWO hops. Martin Packer (talk) 14:16, 22 June 2008 (UTC)
- OK, that might make sense in the Series z aspect, but not in computing general. How cache is named in other systems doesn't reflect how it's implemented, caches can be private, shared on a chip level or shared off die. They are still 1, 2 or 3. While L1 seems to be private in all cases I'm aware of, L2 and L3 can both be shared or private in regard to a processor core. Until now, there's just the hierarchy that mattered, not if they are shared with other recources in the system or is implemented on die or off die. Look at the QorIQ P4080 from Freescale. It also has private L1 and L2, and L3 that's shared across a "book". That book is just implemented on a single die. How this architecture is implemented in silicon or packaging is not the point. Naming the L2 cache "L1.5" just confuses things on a scale larger than z9 vs z10. -- Henriok (talk) 15:10, 22 June 2008 (UTC)
- (This is why I have little desire to work with computers on the architecture level :) I've done some reading and here's what I've found. There is such a beast as an L1.5 cache and it is an intermediary cache between L1 and L2 (Architectural support for thread level speculative execution & US Patent 6910104 - Icache-based value prediction mechanism are a couple sources that mention it). This is definitely an area of confusion between press articles and the technical documentation that is usually published by IBM, with the press referring to L1, L2 and L3 and IBM referring to L1, L1.5 and L2. Perhaps it would be best to explain the differences in terminology in the article and cite press & IBM sources for the sizes: L1 = 64KB instruction, 128KB data; L1.5/L2 = 3MB per core; L2/L3 = 24MB shared. —Preceding unsigned comment added by TreyGeek (talk • contribs) 19:57, 22 June 2008 (UTC)
- Then surely it's a typo where it says "Each core has a 64 KB L1 instruction cache and a 128 KB L2 data cache". That "L2" should be "L1". Theodore.norvell (talk) 11:04, 5 January 2009 (UTC)
- Thank you for noticing that. You are correct on the typo and I've corrected the article. --TreyGeek (talk) 16:14, 5 January 2009 (UTC)
- Then surely it's a typo where it says "Each core has a 64 KB L1 instruction cache and a 128 KB L2 data cache". That "L2" should be "L1". Theodore.norvell (talk) 11:04, 5 January 2009 (UTC)
- (This is why I have little desire to work with computers on the architecture level :) I've done some reading and here's what I've found. There is such a beast as an L1.5 cache and it is an intermediary cache between L1 and L2 (Architectural support for thread level speculative execution & US Patent 6910104 - Icache-based value prediction mechanism are a couple sources that mention it). This is definitely an area of confusion between press articles and the technical documentation that is usually published by IBM, with the press referring to L1, L2 and L3 and IBM referring to L1, L1.5 and L2. Perhaps it would be best to explain the differences in terminology in the article and cite press & IBM sources for the sizes: L1 = 64KB instruction, 128KB data; L1.5/L2 = 3MB per core; L2/L3 = 24MB shared. —Preceding unsigned comment added by TreyGeek (talk • contribs) 19:57, 22 June 2008 (UTC)
- OK, that might make sense in the Series z aspect, but not in computing general. How cache is named in other systems doesn't reflect how it's implemented, caches can be private, shared on a chip level or shared off die. They are still 1, 2 or 3. While L1 seems to be private in all cases I'm aware of, L2 and L3 can both be shared or private in regard to a processor core. Until now, there's just the hierarchy that mattered, not if they are shared with other recources in the system or is implemented on die or off die. Look at the QorIQ P4080 from Freescale. It also has private L1 and L2, and L3 that's shared across a "book". That book is just implemented on a single die. How this architecture is implemented in silicon or packaging is not the point. Naming the L2 cache "L1.5" just confuses things on a scale larger than z9 vs z10. -- Henriok (talk) 15:10, 22 June 2008 (UTC)
- I think the "Level 1.5" name came about because it's also a 1-per-processor cache, just like the Level 1 cache. What we call "Level 2" is per book, with links to the caches in other books. By the way in z10 we have links to ALL the other books, so we don't have the z990 / z9 phenomenon of some L2 caches being only accessible by TWO hops. Martin Packer (talk) 14:16, 22 June 2008 (UTC)
- I think it's clear that IBM uses the 1, 1.5 and 2 moniker for what the rest of the world uses 1, 2 and 3 for. The current Red Books on z10 uses this naming scheme.[1] I can only speculate why IBM does this, but it's probably a way to indicate that "L1.5" faster than usual "L2". But as cache hierarchies go, I can't find any technical difference. If we were to use IBM's way of naming things, we'll have to dedicate a portion in this article to sort things out. -- Henriok (talk) 14:12, 22 June 2008 (UTC)
- All I can tell you is that the announcement foils talk of levels 1, 1.5 and 2. Now whether this is in fact a deviation from standard nomenclature or not I can't say. What I can say is that 1 and 1.5 are one per processor and that 2 is per book. My hesitation on an extensive rework was that I'm not sure what the actual cache sizes are. I note the mention of Charles Webb's name. His foils came out about a year before the z10 machines (and the processors this article is about) were announced and shipped. Terminology may have changed. Actually I don't much mind about the nomenclature. But if I can find something definitive - which one can't call Charles' pitch - I'll try to reference it. Martin Packer (talk) 13:32, 22 June 2008 (UTC)
- There are three levels of cache as TreyGeek noticed. I don't think the introduction of the term "L 1.5 cache" would satisfy anyone but the amrketing folks at IBM. I can't find any reason for this labeling. There are three levels, 1, 2 and 3. So MartinPacker's edit is wrong. The 24 MB off die cache is of the third level and is shared by all cores on an MCM, hence L3 cache. The L2 cache is 3 MB, is on-die and is private for the specific core. -- Henriok (talk) 13:17, 22 June 2008 (UTC)
Instructions
editSome of the new (and old) instructions in the IBM System z10 are not implimented on the z6 chip but are simulated by code running on it. The reference to new instructions should be corrected to reflect what is actually implimented on the chip, or made less specific if those data are not available. Shmuel (Seymour J.) Metz Username:Chatul (talk) 12:48, 3 September 2010 (UTC)
- I'm not sure what you are pointing out is incorrect. I see where the article states that there are 50 new instructions added to the z/Architecture since the z9 chip. However, I don't see where it states that it is implemented in hardware. Am I missing something? --TreyGeek (talk) 14:09, 3 September 2010 (UTC)
- It's at best misleading. especially since the z9 BC and z9 EC are systems rather than processors and the millicode is not part of the z6 chip. How about Additions to the z/Architecture on the System z10 from the previous System z9 include:? Shmuel (Seymour J.) Metz Username:Chatul (talk) 19:54, 3 September 2010 (UTC)
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