Talk:Logical partition

References

References can be found here [1] —Preceding unsigned comment added by 91.152.200.56 (talk) 12:10, 2 November 2007 (UTC)

Not 1972, etc.

IBM introduced the terms LPAR and PR/SM on the 3090, long after the cited date of 1972. The LPAR support differed from the early CP-67, Virtual Machine Facility/370 and Virtual Machine Facility/System Product in that it was bundled with the processor and didn't offer the user controls of the full VM packages.

As part of any article cleanup, the text copied from references should be properly attributed. Shmuel (Seymour J.) Metz Username:Chatul (talk) 22:22, 30 June 2010 (UTC)

IBM only?

This article deals with topics that are present also in other vendors (e.g. HP vPAR) but it seems that it only talks about IBM. — Preceding unsigned comment added by 151.99.187.181 (talk) 11:44, 12 March 2013 (UTC)

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Picture deleted?

What happened to https://i.stack.imgur.com/R0K32.png ? — Preceding unsigned comment added by 84.147.35.23 (talk) 07:51, 26 May 2018 (UTC)

File:Https://i.stack.imgur.com/R0K32.png

That appears to be about disk partitioning which, although the term "logical partition" is used in the diagram, isn't the same thing. Guy Harris (talk) 01:32, 28 April 2023 (UTC)

Hardware beyond SIE?

@Guy Harris: The edit Special:Permalink/1152075614 has the comment An IBM Systems Journal article on PR/SM suggests it's implemented with low-level hardware and microcode at a level very different from the level at which CP runs. I'm not aware of any hardware, microcode or millicode support for VM/XA beyond SIE. Is that article available online? My suspicion is that the "hardware and microcode" it is referring to is just SIE. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 01:54, 28 April 2023 (UTC)

The paper is

Borden, T. L.; Hennessy, J. P.; Rymarczyk, J. W. (1989). "Multiple operating systems on one processor complex". IBM Systems Journal. 28 (1). IBM: 104–123. doi:10.1147/sj.281.0104. ISSN 0018-8670.

and it says:

PR/SM is an optional feature on the IBM 3090 Model E and ES/3090(TM) Model S processor families that allows a single processor complex to support the concurrent execution of multiple operating systems. It consists of special hardware and microcode that can be invoked and controlled in either of two ways: directly through the machine console (hardware logical partitioning) or indirectly under software control by the VM/XA SP control program.

and later indicates that

Logical partitioning is a new mode (LPAR) for the IBM 3090E and ES/3090S processor families that is selected at power-on reset (POR) of the processor complex. With the PR/SM feature installed, 3090E and ES/3090S processors have three basic modes--System/370, 370-XA or ESA/370, and a new LPAR mode.

In LPAR mode, main storage and expanded storage are subdivided into contiguous areas with 1-megabyte granularity and allocated to each of the partitions such that each partition appears to have a 0-origin for its storage. All storage addresses used in the instructions or channel program addresses of a partition are relocated by the processors and channels and checked to ensure that they are in the range of physical storage allocated to the partition...

I'm guessing that involves hardware in the real-addresses-to-memory path, so that there's little or no per-memory-access overhead, plus microcode to set up the hardware and, perhaps, to allow software hypervisors to set it up, as per the "indirectly under software control"quote above. There's other software to partition devices, which may involve the microcode for the I/O instructions (I don't see anything to indicate whether real addresses in CCWs etc. get run through hardware or are translated by microcode). There's also a dispatcher to handle switching which logical processor's code a physical processor is running.

They don't mention any software involved in LPAR mode, only in the "VM/SP uses some LPAR facilities" (V=F) mode. I don't know whether there's a small hidden software hypervisor sitting atop the hardware and microcode or not; it looks as if manaaging LPARs is up to the service processor. They also don't seem to indicate that SIE is involved with LPARs, just with, perhaps, V=F VMs in VM/SP. Guy Harris (talk) 06:12, 28 April 2023 (UTC)

However, this slideshow, from IBM about System z virtualization, speaks of LPARs as using SIE-based virtualization with an LPAR hypervisor. However, I have the impression that none of the z/Architecture processors (and most if not all of the CMOS ESA/390 processors?) have traditional microcode, they just have PALcodemillicode - which seems similar to System Management Mode in some ways, with code running in an extra special mode underneath not only user-mode code but OS code - so it might be similar to a software hypervisor, but one that comes from system firmware (just as the SMM monitor on a PC is part of the system BIOS/UEFI firmware) rather than being booted.

So I suspect that current LPAR hypervisors are "software" in the sense that they mostly consist of S/390 or z/Architecture machine instructions, possibly with some platform-dependent millicode-mode instructions, rather than "firmware" in the sense of CPU microinstructions. That code might even be adaped from VM CP. That "software" may be more like ROM monitor code than code loaded from a boot medium to which OSes have access, though.

That may not be the case for earlier machines; there might be CPU microcode doing all the functions not done directly by hardware, including CPU dispatching. Adapting CP code into horizontal microcode might be a heavier lift than adapting it to millicode (unless the traditional horizontal CPU microcode in 3xxx machines was written in something resembling PL/S or PL.8 or... so that a compiler could do much of the heavy lifting). Guy Harris (talk) 08:28, 28 April 2023 (UTC)

LPARs are, and always have been, implemented with a special version of CP (initially from VM/SP R6) that relies on the same SIE instruction that VM/XA through z/VM do. The implementation of SIE varies from processor to processor, and definitely involved microcode on the early models. There was a period where some models had both microcode and millicode, but I don't know whether that is relevant to SIE. The key statement in the slideshow is Hardware does most of the virtualization (SIE architecture); the hardware assist is in the SIE implementation. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 13:10, 28 April 2023 (UTC)

There's also

"IBM z13 firmware innovations for simultaneous multithreading and I/O virtualization". IBM Journal of Research and Development. 59 (4/5). IBM: 11:1-11:11. July–September 2015. doi:10.1147/JRD.2015.2435494. ISSN 0018-8646.{{cite journal}}: CS1 maint: date format (link)

seems to speak of the PR/SM hypervisor as being separate from millicode, so maybe, all the way back to the original PR/SM, it's some flavor of System/3x0 code running in a mode that's more privileged than bare-metal supervisor mode but less privileged than millicode mode (on machines with millicode), from some walled-off area of main storage (HSA?), loaded from some machine-dependent medium.

And this slideshow from IBM has a pyramid with "Hardware", "Millicode", "i390 Code", and "LPAR Hypervisor (PR/SM)" all below the "z/Architecture Level" in System z. So I guess "microcode" is a funny word at IBM (as if we didn't already know that from System/38, where "microcode" in "vertical microcode" is a legal term rather than a technical term, done in order to keep IBM from having to offer low-level system cde to clone makers, according to Frank Soltis). It appears to mean "anything that's not purely hardware and that's below the architecture level", and includees stuff that's somewhat machine-code-ish, including millicode, i390 code (and i370 code), and the LPAR hypervisor. Guy Harris (talk) 18:07, 28 April 2023 (UTC)

As for "i390", this paper:

"Open-standard development environment for IBM System z9 host firmware". IBM Journal of Research and Development. 51 (1.2). IBM: 195–205. January 2007. doi:10.1147/rd.511.0195. ISSN 0018-8646.

says

System z host firmware consists of two levels. The first is the lower-level millicode layer. This layer is written in assembly language and runs directly on the z9* processor hardware. It is used to implement performance-critical functions or functions that require direct control of the underlying hardware structures. The millicode layer has to be adjusted for each new System z hardware generation. The second firmware level, which runs on top of the millicode layer and can use functionality provided by the millicode, is the higher-level internal 390 (i390) code. It is written primarily in PL8 or C and implements functions that are less performance-critical or too complex to code in assembly language. An advantage of the i390 code layer is that most parts of it do not have to be adjusted for each new System z processor generation because the underlying millicode layer deals with most of the hardware-specific handling. (See [1] for a discussion of the firmware stack running on a System z.)

"[1]" is

"z/CECSIM: An efficient and comprehensive microcode simulator for the IBM eServer z900". IBM Journal of Research and Development. 46 (4.5). IBM: 607–615. July 2002. doi:10.1147/rd.464.0607. ISSN 0018-8646.

which again speaks of two levels of "firmware", millicode and i390, and the LPAR hypervisor running atop those and below the OS, so maybe that's a third level of, well, whatever IBM considers "stuff running below the OS". That paper points to

Miirgner, Jurgen; Schwermer, Hartmut (1989). "High Level Microprogramming in 1370". In Spruth, Wilhelm G. (ed.). The Design of a Microprocessor. Springer Nature. pp. 303–316. doi:10.1007/978-3-642-74916-2. ISBN 978-3-642-74916-2.

which is about the "Capitol" chip set, designed in Böblingen, used in the ES/9370 systems, which has an i370 mode (as S/390 wasn't out yet). That processor runs some 370 instructions directly in hardware, runs some with vertical microcode also directly run in hardware (same hardware, but the instruction format is different, so two types of instructions run directly in hardware), and probably runs i370 instructions either directly in hardware or in vertical microcode. Apparently the vertical microcode format is similar to that of the 4361 and the 9370-90.

They don't speak of PR/SM.

TL;DR: IBM doesn't have a consistent nomenclature for everything below the ISA layer, and they may sometimes call it "microcode" even if it more or less just looks similar to S/3x0 machine code, so maybe the LPAR hypervisor was called "microcode" even though it doesn't particularly resemble microcode. Guy Harris (talk) 18:52, 28 April 2023 (UTC)

But a citation would still be good. Guy Harris (talk) 19:33, 28 April 2023 (UTC)

Both more citations and more wordsmithing to fill in the details would be welcome. That said, although the 3090 allowed the customer the option of running in S/370, S/370-ESA or PR/SM mode, current machines only support PR/SM. The only OS that runs on bare metal is the CP version used by PR/SM. z/OS, z/VM et al can only run in an LPAR. PR/SM uses the preferred virtual machine option of SIE; it does no paging of its own for the guest memory. -- Shmuel (Seymour J.) Metz Username:Chatul (talk) 20:01, 28 April 2023 (UTC)

Notes