Talk:PCI Express/Archive 2009

Graphics PCIe

There is a lot of evidence that nVIDIA was cheating with Graphics PCIe. At least latest tests of Micron (see Micron presentation of SSD card) an several reports that nVIDIA boards do not suppot more than 1 ioDrive (well, you may install even four, but no combination allow more than 1GB write to memory or read from memory). The citated site only collect spread about information into one place. BTW, you may contact SAPPHIRE whith a queaston: "will the installation of two Radeon HD 4850 X2 in shared slots on Intel m/b with PCIe v.1.1 only or x58 m/b degrade the performance?" - the answer will be "no" The same question about nVIDIA m/b will result in "yes".

See http://www.engadget.com/2008/12/05/video-microns-washington-pcie-prototype-ssd-card-is-wicked-qui/ for Micron test and pay attention that ONE prototype board runs at 800MB/s and TWO - at 1000 - tests were run on nVIDIA m/b :) ! Stasdm (talk) 20:07, 13 December 2008 (UTC)

I suggest that a list of compatibility should be made for this purpose. Also it's not only nVidia... in the article it's clearly suggested "hence the still often met recommendation not to use RAID/LAN cards in the "Graphics" slots)". Thing is that while searching for an answer to the "RAID card in x16 slot" problem I found a guy that uses an ASRock mainboard with an ULi M1695 NB and ULi M1567 SB. His PC POSTs... but fails to load XP. If by any chance it's a driver related issue and it's fixed, people with such chipsets might actually take advantage of their x16 slots. Also what about 790X and 790FX chipsets? Are they good? Are they not? Seeing how mainstream mainboard manufacturers skip adding x4 and x8 for the older PCI slot... or four x16 out of which two might actually be used it might be a good addition or reference to the article. Or if there are other suggestions to this... links to other wiki articles it'll be good to link to them.

Em27 (talk) 07:19, 24 December 2008 (UTC)

OCZ representative on one of the threads in the OCZ forum SSD drives section states that 790X HT may be overclocked to 1.8 GB/s from 1.2 native. Any more evidence needed that up to 3 nVIDIA bords working full speed can nicely share 1.2GB/s with 350 MB/s SSD (in RAID0)? Stasdm (talk) 07:36, 15 January 2009 (UTC)

One badly-written personal web page does not constitute "a lot of evidence". I believe citing your own site as a source violates the Original Research rules. If you google for "nVIDIA PCI Express implementation", "nVIDIA non-standard PCI express", "Graphics PCI Express" and other related phrases, there is no coverage of this so-called "cheating" by any reliable source. Using the Micron SSDs as a benchmark of HT bandwidth is just ludicrous - there may be differences in the performance of the SSD itself depending on the PCI Express chipset it is communicating with, the benchmark software being run, and the wear leveling state of the SSD itself. I recommend removing the "Graphics PCI Express" section until more reliable and technically correct sources can be cited for the material. -Andrew B —Preceding unsigned comment added by 72.92.154.67 (talk) 08:43, 27 December 2008 (UTC)

You had to look better!

1. Intel 5040 chipset manual states that PCIe x16 line of the chipset supports only 2.5GB/s throughput, but fully support work of "Graphics PCIe" devices - so "Graphics PCIe" is no faster than 0.525 of PCIe v.1.1, as DX5040 board may support up to four graphics cards on separate 3D use.

2. PCIe is a common standard. If the divice can work in non-graphics slot and cannot in "graphics" one means that the "graphics" slot does not confirm to the standard, nothing else.

3. Lot of forums threads dealing with RAID use state that it is impossible to get more than 1.0-1.2 GB/s from nVIDIA chipsets, while same implementations on Intel and AMD chipsets shows the expected results (look in the alredy cited OCZ forum for example).

I do not think that nVIDIA-related fellow may have any right to criticize anti-nVIDIA statments w/o backing arguments, which are really not existent Stasdm (talk) 07:50, 15 January 2009 (UTC)

Fixes

I don't want to make incorrect changes but it seems that the throughput stated in different places in the article is wrong. For example: "First-generation PCIe is often quoted to support a data rate of 250 MB/s in each direction, per (x1) lane. This figure is a calculation from the physical signaling rate (2.5 Gbaud) divided by the encoding overhead (10 bits per byte.) This means a sixteen lane (x16) PCIe card would then be theoretically capable of 250 MB/s * 16 = 4 GB/s in each direction."

I think PCIe first generation one lane is 125 MB/s in each direction = 250 MB/s (2.5 Gb/s) total per lane = 1.25 GHz clock speed (1.25 Gbps per lane per direction).

This was a source of confusion for me and I think it should be clear throughout the article.

It should be: First-generation PCIe supports a data rate of 125 MB/s in each direction, per (x1) lane. This figure is a calculation from the physical signaling rate (1.25 Gbaud) divided by the encoding overhead (10 bits per byte.) This means a sixteen lane (x16) PCIe card would then be theoretically capable of 125 MB/s * 16 = 2 GB/s in each direction. This throughput doesn't take into account overhead which is around 32 bytes (header) per packet with each packet payload being between 32 bytes (data) and 2 kilobytes (data).

--Nachumk (talk) 12:09, 18 January 2009 (UTC)

Power ratings ?

Can someone please provide the power ratings for PCI-E slots ? Thanks ! --Xerces8 (talk) 07:20, 24 April 2009 (UTC)

Alternate form factors section

This section begins with the line:

There are several other expansion card types derived from PCIe. These include:...

This statement is followed by a list that includes ATCA and AMC form factors.

I'm not sure what the author is trying to say here. ATCA is not "derived" from PCIe. The only fixed point of commonality between PCIe and ATCA/AMC is the low-voltage differential signaling physical layer. ATCA is protocol-agnostic above the LVDS layer. The ATCA/AMC standards recommend connector mappings for multiple protocol options - including PCIe - but connectors and blades are completely different from PCIe boards. See PCIMG.org for the free "short-form" ATCA specification Ged Davies (talk) 03:13, 16 May 2009 (UTC)

Rambus

71.7.248.200 (talk) 20:40, 29 May 2009 (UTC) The article on Rambus says it created the PCI-E interfaces, but Rambus is not mentioned at all in this article on PCI-E. Rambus has had a questionable history as a company, but for completeness of facts, shouldn't it be mentioned here that Rambus was the creator of the PCI-E interface? Personally, I'm not sure what "It also developed PCI-E interfaces" (quote) from the Rambus article means as far as their relationship to PCI-E implementations and standards go... so maybe someone with this knowledge could update this article (and maybe also the Rambus article) to better describe how Rambus relates to the history and current status/licensing of PCI-E technology.

Based on their press releases, Rambus has developed a physical layer (PHY) implementation (two actually) that is compliant with the PCI-Express standard. They did not single-handedly create PCI-Express. I believe this is what the Rambus article is trying to communicate. Given that this article does not discuss any other implementations of the standard (except a bit on the Intel P35 chipset, which should probably be moved to the P35 article), I don't see any need to mention Rambus here. — Aluvus t/c 01:39, 30 May 2009 (UTC)

status

quad gpu systems run on two PCI-e slots with dual gpu cards there are at most three cards —Preceding unsigned comment added by 24.149.34.216 (talk) 00:59, 20 May 2009 (UTC)

This section should be removed. It does not fit an encyclopedic type definition. Will someone be available to update this section for everyday changed in the status? I believe not.70.244.234.220 (talk) 14:12, 24 June 2009 (UTC)

6-pin PCIe Supplementary Power Connector

The 3x2-pin power connector found on many PCIe graphics cards is never mentioned in this article. Should it be?

Etoombs (talk) 21:59, 11 July 2009 (UTC)

PCI Express 3.0

The PCI Express 3.0 section reads like an industry press release. It's too slick to be unbiased IMO. -- BlindWanderer (talk) 14:52, 28 August 2009 (UTC)

Content needing citations or correction

In the Speed section, the table "Specs for each PCIe generation per lane" has a column titled Clock speed, which appears to be half the bit rate per lane. I am on the PCI-SIG Electrical Working Group and the Serial Enabling Group and I'm quite familiar with the PHY specs, and at least at the moment, I don't know what that Clock speed refers to. PCI-Express has a system clock that is 100MHz (modulated for SSC, if enabled) for all generations. I'd like to see a reference cited for that the Clock speed column. Also, "Gen2" added the 5GT/s speed as well as several other capabilities, and a device can be Gen2 due to having those other capabilities but operate only at 2.5GT/s. However, it is so widespread to talk about 5GT/s as "Gen2 speed" that that's OK - but I would like the article to clarify that usage. JoeS LeCroy (talk) 16:34, 31 August 2009 (UTC)

"typical applications" = USB or Ethernet?

I found this in the transaction layer part:

But in more typical applications (such as a USB or Ethernet controller), the traffic profile is characterized as short data packets with frequent enforced acknowledgements.

But GPUs are the most typical applications for PCIe today, so there should also be something about the typicla traffic profile for PEG slots. --MrBurns (talk) 15:45, 1 September 2009 (UTC)

While GPUs are a big user of PCIe and probablly the biggest user of PCIe cards there are a lot of PCIe ethernet and wi-fi controllers arround, it's just that most of them are soldered to motherboards (in the case of ethernet and sometimes wi-fi) or on mini cards rather than on full size cards. USB OTOH seems to mostly be integrated into the chipset. Plugwash (talk) 17:25, 1 September 2009 (UTC)

Hotplugging

In the box, the article says: "Hotplugging? Yes, if ExpressCard or PCI Express ExpressModule." It is not correct this way. Whether a port supports hotplugging depends (only) on the chipset. Normally (as one would expect) this is enabled for ExpressCard slots (which is just a physical variant of PCIe ports). It can also be enabled for all other PCIe-style ports but normally isn't with the exception of the ports used for Express Modules. In case a port is enabled for hotplugging every card that fits into the slot can be hot-plugged into this port.--Sixot (talk) 17:25, 8 September 2009 (UTC)

OVM / VVM Methodology to Design and verify the PCIe

Importance of the System Verilog Assertions to verify the PCIe protocols on a chip / SoC —Preceding unsigned comment added by Xilinx.fpga (talk • contribs) 08:52, 11 October 2009 (UTC)

PCI Express 2.0

"PCI-SIG announced the availability of the PCI Express Base 2.0 specification on 15 January 2007.[16] PCIe 2.0 doubles the bus standard's bandwidth from 0.25 GByte/s to 0.5 GByte/s, meaning a ×32 connector can transfer data at up to 16 GByte/s for both videocards (SLI 2×, etc.). PCIe 2.0 has two 32-bit channels for each GPU (2×16), while the first version only has 1×16 and is operating at 2 GHz "

This makes no sense at all as an intro to this section. This is the second time PCI-SIG is mentioned in the article; neither of which explain what or who PCI-SIG is. The quoted section above states "for both videocards"; either this was copied from another article, or the writer has no idea how to write quality essays for inclusion in encyclopedic articles. There is no previous mention of video cards, and does the PCI-e 2.0 only pertain to only video cards?

In all actuality this entire article is poorly written. After reading it, I gained no more knowledge about PCI-e than I had before. Wikipedia has a bad reputation in acadamia, this article exemplifies the reason no sane Professor would accept Wikipedia as a reference. —Preceding unsigned comment added by 70.244.234.220 (talk)

LOL, but "PCI-SIG" is already defined earlier in the article as "PCI Special Interest Group." But I agree with you on most of what you said. Being an engineer, I made corrections therein; but of course, the rest needs work by one who is at least a technical writer, if not an engineer. What you said is the reason I stopped editing. Mdoc7 (talk) 04:00, 28 October 2009 (UTC)

Rated speed is bidirectional?

Is the speed of for example "v1.x: 250 MB/s" per direction or the sum for both direction? IOW does it go 250 MB/s in one direction and 250 MB/s in other at the same time, or is it 125+125=250 ? I can not read that out from the article (reading the capacity related parts) Xerces8 (talk) 22:06, 21 September 2009 (UTC)

It is not 125+125=250MB/s. 250MB/s is the rate for one direction, bidirectional or not. Mdoc7 (talk) 03:30, 30 October 2009 (UTC)

Original research under PCI Express 2.0

The mention of Intel P35 not being the first Intel PCIe 2.0 chipset and subsequent content seems to be phrased in a way that represents original research, despite citing supporting evidence from a primary source (which I have not reviewed, for current lack of time). I have tagged the content with Or but left it in place, as part of a quick section edit. This comment is intended as a starting point for potential discussion of this action. Anyone can feel free to fix or delete the material. 69.181.227.133 (talk) 22:23, 17 December 2009 (UTC)

electric power supply (Watt) is missing

Hello

I'm missing the values of the electric power supply (Watt) in this article.
Because my English is not the best, please add this (in well formed sentences or as a table):
PCIe 1.x/2.x:
75 Watt PEG-Slot (x16) +75 Watt 6Pin +150 Watt 8Pin = 300 Watt max
25 Watt non PEG-Slot and 10 Watt Low-Profile

PCIe 3.0 = ? Watt

Thx
—Preceding unsigned comment added by MrX1980 (talk • contribs) 11:09, 31 December 2009 (UTC)