Talk:PowerPC G4

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Motorola do not refer to their chips using either G3/G4/G5 moniker instead using model numbers. It is Apple that decides which chips belong to which G series - surely this should be reflected here? --DamienG 00:45, 31 Aug 2004 (UTC)

I agree. Article should make a point of the fact that "G4" is an Apple designation, not a Motorola or IBM designation (although they're happy to use the name). IBM got the benefit of pick when Apple built the G5, leaving all the comparable Motorola (Freescale) parts with a "G4+" designation in the data sheets.

The article mentions that the Freescale 7447A is a G4, but it's misleading since the 7447A is a much higher performance device than the original G4, the 7400.

Dennis 00:37, 23 Dec 2004 (UTC)

The "Gn" naming scheme was originally an internal code-naming scheme for the various generations of PowerPC processors. Apple used the scheme for marketing purposes, but at one time these were actual internal designations. (Compare to Intel's use of names like "Merced" and "Banias.") Motorola does sometimes use "G4" to refer to the PowerPC 7xxx series of processors in its marketing documents, probably to simplify the naming scheme, and to capitalize on the publicity from Apple. (See the PowerPC Sales Fact Sheet, "PowerPC Processors At-A-Glance," for an example.) Exia 17:24, 20 February 2006 (UTC)

bus width

"...the width of the bus is such that the vector units (which process Altivec) are never starved for data as some have erroneously claimed."

I'd delete this right away as utter nonsense, but I get the feeling the author didn't mean it literally (of course a 1.67 GHz CPU can be starved by 167 MHz bus), and I'd like them (or someone else) to expand it.

Future Section Changed

I updated the Future section to reflect recent changes in Apple's computer lineup... If anyone would like to improve upon the grammer in the edited sections please feel free. Thanks ^_^

About AltiVec and non-G4 processors

The design section is heavily geared towards AltiVec which seems reasonable, but there's also a paragraph which discusses Alitvec implementations in other processor designs. I don't think this fits into this article and I think we'd better leave it for the article about AltiVec. -- Henriok 18:07, 4 July 2006 (UTC)

Huh? (sentence makes little sence to me)

"Motorola's inability in 1999 to obtain yields of the 7400 series at Apple's desired clock speed caused Apple to do an abrupt about-face on sales of its Power Mac G4 tower series of computers". What exactly is that supposted to mean?, I've never heard of this (slang?) expression before. Could someone who understands please rewrite that sentence? --220.233.211.189 17:07, 5 August 2006 (UTC)

Good point.. The event in question is that Apple promised machines in 400/450/500 MHz, but ended up getting hardly any 500 parts, so they downgraded the entire PowerMac G4 line to 350/400/450 models. Apple then hired IBM as a second source since Motorola had a hard time to keep up with demand. -- Henriok 19:46, 5 August 2006 (UTC)

Rename

I'd like to propose a rename of this page. "G4" was the codename for this family processors and Apple used it in its marketing, neither case should have any bearing on what this page is called. The proper name for this article shoule be something like "PowerPC 7400", "PowerPC 74xx" or "PowerPC 7400 family". Even "PowerPC e600" would be more appropritate imho, since this is the new name for this processor core. I'd like commets on the suggested names, and other variations are welcome. I also will make the same proposition regarding the PowerPC G3 article, with the same argumentation. Please comment there too. -- Henriok 11:01, 2 November 2006 (UTC)

L3 cache

This part is not quite correct:

"The 7457 has an additional L3 cache interface, supporting up to 4 MB of L3 cache, up from 2 MB supported by the 7455 and 7450. However, its frequency scaling stagnated when Apple chose to use the 7447 instead of the 7457, despite that the 7457 was the L3 cache-enabled successor to the L3 cache-enabled 7455 that Apple used before."

According to the datasheet, the L3 interface supports 1, 2, or 4 Mbytes of external SRAM for L3 cache and/or private memory data. For systems implementing 4 Mbytes of SRAM, a maximum of 2 Mbytes may be used as cache; the remaining 2 Mbytes must be private memory.

Cannaya (talk) 02:27, 30 May 2020 (UTC)