Talk:Reconfigurable computing

"Reconfigurable Computing" vs "Reconfigurable System"

The reason why one should not change reconfigurable computing to reconfigurable system is to understand what exactly reconfigurable computing addresses. To baseline; a computer system is defined as an organised collection of hardware and software components designed to manipulate data in a '''''''meaningful''''''' manner. An abstract way to model such computer systems is to use a method called computer system model (CSM). CSM is composed of three architecture types providing clear abstraction level views to a computer system. These architecture types are known as computer architecture (CA) which is everything to do with the CPU, implementation architecture (IA) which is everything to do with the platform and software architecture (SA) also known as system architecture and deals with the software domain of a computer system.

Computer Architecture addresses the organisation and design of the CPU, a basic CPU is composed of two domains which are; Control Path and Data Path. However, these two domains are heavily influenced by the computational configuration adopted. There are two computation configurations which are; Temporal –compute in time and Spatial –compute in space. Examples of temporal solutions would be; Pentium, Opteron, Xeon, Itanium, Power and SPARC. And examples of spatial would be ASICs.

Without delving deep into CPU design a short synopsis would be; CPUs that use a temporal configuration generally has a large control path over the data path. As an example the Itanium McKinley has a control path of ~71% and a data path of ~7.4% the remaining area is used for miscellaneous circuitry. Whereas an ASIC, the ideal spatial solution will use ~80% data path and 15% control path. Spatial solutions like ASICs offer greater performance/watt/cycle than there temporal solutions, which, temporal solutions counteract this by offering better application flexibility through programmability. Reconfigurable Computing (RC) introduces a third type of computation configuration which is a mix between temporal and spatial. How the blend of this mix is done depends on the innovation of the RC. As I described earlier computational configuration influences the CA’s control and data paths, and RC is a new form of computational configuration thus, RC is not a computer system it is in fact an architectural form of CA. Which means the best suited name is Reconfigurable Computing and not Reconfigurable System.

User:Lucid57 21:43, 25 March 2010 (UTC)|86.139.83.167|22 September 2005

Terminology

I converted the terminology into a table and moved it into the near bottom. Having it as sections made it hard to get an overview of the article. BTW, this is the first time I've seen an article have a whole terminology listing, is it really needed or could we link to relevant terms instead? Henrik 20:33, 28 February 2006 (UTC)

Problems with the Article

1. The paper talks about "Estrin" hybrid computers. As far as I am aware this is not a commonly used term in reconfigurable computing. I would recommend it is not used unless anyone can provide proof that it is a current and widespread term.

2. Too much marketing material is reproduced here in relation to SRC and Mitrionics. There are a lot of players in this market, loads will die off and loads more will emerge. This article should be futureproofed by toning the down the constant references to current market players. It will also lessen the temptation for the market players themselves to increase the amount they're referred to in this article.

3. Only one author has ever used the term "Reconfigurable Computing Paradox", so it seems like it shouldn't be used here until it gains more currency in the greater research community.

Generally the article is not in a good shape. I think we need to start discussing a new plan for a total rewrite of this article.

82.46.67.130 17:53, 26 July 2007 (UTC)

"Gerald Estrin's landmark paper proposed the concept of a computer made of a standard processor and an array of “reconfigurable” hardware." This is just flat wrong. Estrin created a system whereby you could add an instruction to the instruction set by putting a card in a card cage. If you want to say Estrin's paper is the "landmark" paper in reconfigurable computing you might as well go back to John von Neumann (Estrin studied under von Neumann). Estrin's name first comes up in a Scientific American article. In that same issue was an ad by Virtual Computer Corporation, Xilinx and Marshall Electronics about the H.O.T Works development system for only $995.00. 66.166.202.162 (talk) 21:57, 12 March 2008 (UTC) Steve Casselman

[1] J. Villasenor, W. H. Mangione-Smith, "Configurable Computing," Scientific American, pp.66-71, June 1997.

In the section "Examples for hybrid computers" it is interesting to note that DRC is not mentioned when Cray replaced the Octigabay system with RPUs from DRC Computer (www.drccomputer.com) (www.cray.com/Assets/PDF/products/xt/CrayXR1Blade.pdf). In 1986 I wrote my first paper which talked about taking C, compiling it down into a series of bitstreams, and loading them one after the other. In 1989 I received a phase I SBIR (http://tech-net.sba.gov/tech-net/public/dsp_award.cfm?IMAwrdSeqNmb=9808) to work on the hardware to do that. I filed my first patent in 1992 (US5684980). I invented the FPGA in the Opteron socket 16 days after the Opteron was announced. While out trying to raise money we talked to a VC who had Steve Wallach do some due diligence and talk to some of our customers. He then founded Convey as the "first hybrid core computer." I have not edited any of the pages in this section because I have been at it for so long that it would not be right for me to do so. However I can't think of anyone else who has been at it so long and is still making significant contributions to the field. Look at http://www.commacorp.com/management.html where I am putting some of the documents needed to prove I'm one of the founder of the field. Check out my proposal from 1987. It's exactly what we are doing today.

In no way did Estrin invent reconfigurable computing. His work was to add instructions to a fix computer's ISA by having a bus (like a PCI bus) and plugging cards in that would add new "instructions" to the existing computers ISA. Reconfigurable computing could not exist until the invention of the FPGA. In reconfigurable computing you reuse the silicon by configuring the fabric over and over again creating a nearly infinite amount of hardware. Estrin's work did not do this and did not foresee this. — Preceding unsigned comment added by 50.141.33.24 (talk) 05:56, 4 September 2015 (UTC) Steve Casselman, 2/26/2010 —Preceding unsigned comment added by 66.166.202.162 (talk) 21:14, 26 February 2010 (UTC)

I put together a presentation of my contribution to reconfigurable computing. https://docs.google.com/presentation/d/1azrWvRj-xehnWt2vkA_6rA4Jo-a3wE0uGgbE5liU_dI/edit?usp=sharing 2600:1702:A20:E790:14F9:9853:E8B8:65A3 (talk) 18:45, 24 April 2018 (UTC)

$1,000 Supercomputer?

http://www.cnn.com/TECH/computing/9906/15/supercomp.idg/ Back in 1999, Starbridge Systems claimed it would have a $1,000 supercomputer for sale within 18 months, and that it would be 60,000 times as fast as a 350 MHz Pentium 2.

What happened? It's been nearly a decade and still no $1,000 supercomputer. Emails to the company haven't been answered. —Preceding unsigned comment added by 72.67.35.214 (talk) 10:05, 5 March 2008 (UTC)

Terminology and Self-Promotion

The terms "flowware" and "configware" are not standard within the field. This is pure self-promotion from Reiner Hartenstein and company. I witnessed him at a conference arguing with other researchers to try to force his terminology, which is rather outdated and meaningless. Just follow the link to Reiner Hartenstein and you will see that there is an excessively long page for someone with only minor notability. Compare this with other academics of similar importance. I think this article should be cleaned up to reflect the consensus of the reconfigurable computing researchers and not of one man.

208.191.58.164 (talk) 12:21, 13 November 2008 (UTC)

I agree, this is self-promotion by Reiner Hartenstein, or Rainier as he spells it on wikipedia. I have marked this page as COI, and I believe the entire Reconfigurable computing as a paradigm shift: Hartenstein's anti machine section should be removed. I've also proposed the anti-machine page be deleted. Dsav (talk) 16:49, 21 April 2009 (UTC)

I like very much this article! I'm not connected in any way with Rainer Hartenstein, but I'm very glad that an expert in the field takes the time to explain the concepts to the non-expert. Maybe I'm a bit biased, because I'm born with something like TRECCANI encyclopedia, where the articles are written by experts, and it's always a great lesson and pleasure to learn from the experts. I absolutely don't mind the use of terms like configware, which renders perfectly the concept. I think that the personal judgement of the person are something due either to envy or poor respect for other's opinion. Finally, as I maybe a bit expert in the field, I can say that it would be a shame not having a large article on "Reconfigurable Computing", which is one of the most important computer technologies nowadays. If you want to have more interesting articles, I think that you should be more inclusive of the many contributions. robg 21:46, 27 July 2010 (UTC) —Preceding unsigned comment added by Robgiorgi (talk • contribs)

FPGA-based programmable, on demand co-processors

"[...]a solution where a softcore activates critical application-specific instructions that are coded in a hardware definition language in the same chip can be a very efficient solution in some cases. An even more powerful solution is the combination of a dedicated microprocessor core and an FPGA in the same chip. Such hybrid solutions are now used in some embedded systems." [1] —Preceding unsigned comment added by Parallelized (talk • contribs) 09:13, 24 July 2008 (UTC)

• http://ddj.com/embedded/207801305 —Preceding unsigned comment added by Parallelized (talk • contribs) 09:32, 6 August 2008 (UTC)

External link

Hello, I'm working for the So-logic company, located in Vienna, Austria, www.so-logic.net. We have developed the FPGA Database application, www.so-logic.net/en/fpga/table/producers. It is the directory of all FPGA families that have ever existed on the market. It is free of charge and available to everyone. We would like to add the link to our database in the Wikipedia external links on this page. Thank you for your time. --Maja Gordic (talk) 15:08, 6 April 2010 (UTC)

I don't think the link should be added. It is not our practice to add links to vendor sites or lists of vendors. See WP:EL for more details on what should and should not be linked. - MrOllie (talk) 15:09, 6 April 2010 (UTC)

I certainly do not think that the link belongs in this article - a device list does not enhance the readers understanding of this topic. If anything, it belongs in the FPGA article, but even that is up for discussion (for better or worse, the discussion is actually taking place here: Talk:Xilinx/Archives/2011#External_link). —Mrand ^{Talk • C} 16:06, 6 April 2010 (UTC)

Preserve major blanking

For reference and to wp:preserve, there has been a big removal of content at this revision. Users interested in the topic may find it useful, and knowledgeable editors may want to review that some of it can be sourced and included back in the article. Diego (talk) 10:09, 24 November 2011 (UTC)

I would like someone else who maybe knows something about the subject to check the removals there. I got alerted by a link to a porn site (I translated it) and multiple links in the same paragraph to a website. I googled blocks of text and found the exact same content on many different sites, as if someone were trying to do a ...what... google bomb or something. It was also lacking sources. B^e——C_ritical 20:25, 24 November 2011 (UTC)

No valid reason given for major blanking. Adding most of the content back. Although I have deleted some portions to wikify the content. Agreed it was a mess. Didn't have to be completely deleted though. Wonderfl ^(reply) 10:45, 25 January 2015 (UTC)

I see problem with that BRAM implementation

Apparently you are feeding the block RAM with 8 different addresses sources . Now how is that going to work? Ebaychatter0 (talk) 05:43, 7 September 2012 (UTC)

Well, this could probably be done with 8 FPGA, each having its own BRAM; i doubt it can be done with 1 FPGA. Ebaychatter0 (talk) 09:55, 7 September 2012 (UTC)

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