Template:AMD Radeon RX 7000M

Model (Code name)	Release date	Architecture & fab	Chiplets	Transistors & die size	Core		Fillrate^[a]^[b]^[c]		Processing power^[a]^[d] (TFLOPS)^[e]			Infinity Cache	Memory				TDP	Interface
Model (Code name)	Release date	Architecture & fab	Chiplets	Transistors & die size	Config^[f]	Clock^[a] (MHz)	Texture (GT/s)	Pixel (GP/s)	Half	Single	Double	Infinity Cache	Size	Bandwidth (GB/s)	Bus type & width	Clock (MT/s)	TDP	Interface

Radeon RX 7600S (Navi 33)^[1]	Jan 4, 2023	RDNA 3 TSMC N6	Monolithic	13.3×10⁹ 204 mm²	1792:112:64:28:56 28 CU	1500 2200	168.0 246.4	96.00 140.8	21.50 31.54	10.75 15.77	0.336 0.493	32 MB	8 GB	256	GDDR6 128-bit	16000	75 W	PCIe 4.0 ×8
Radeon RX 7600M (Navi 33)^[2]					1792:112:64:28:56 28 CU	1500 2410	168.0 269.9	96.0 154.2	21.50 34.55	10.75 17.28	0.336 0.540			256		16000	90 W
Radeon RX 7600M XT (Navi 33)^[3]					2048:128:64:32:64 32 CU	1500 2615	192.0 334.1	96.00 167.0	24.58 42.84	12.29 21.42	0.384 0.669			288		18000	120 W
Radeon RX 7700S (Navi 33)^[4]					2048:128:64:32:64 32 CU	1500 2500	192.0 320.0	96.0 160.0	24.58 40.96	12.29 20.48	0.384 0.640			288			100 W
Radeon RX 7800M (Navi 33)^[5]	Sep 11, 2024			28.1×10⁹ 346 mm²	3840:240:96:60:120 60 CU	2145	560.4	?	71.73	35.87	1.204	48 MB	12 GB	432	GDDR6 192-bit		180 W	?
Radeon RX 7900M (Navi 31)^[6]	Oct 19, 2023	RDNA 3 TSMC N5 (GCD) TSMC N6 (MCD)	1 × GCD 4 × MCD	57.7×10⁹ 529 mm²	4608:288:192:72:144 72 CU	1825 2090	525.6 601.9	350.4 401.3	67.28 77.05	33.64 38.52	1.051 1.204	64 MB	16 GB	576	GDDR6 256-bit		180 W	PCIe 4.0 ×16

^ ^a ^b ^c Boost values (if available) are stated below the base value in italic.
^ Texture fillrate is calculated as the number of Texture Mapping Units multiplied by the base (or boost) core clock speed.
^ Pixel fillrate is calculated as the number of Render Output Units multiplied by the base (or boost) core clock speed.
^ Precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
^ GPUs based on RDNA 3 have dual-issue stream processors so that up to two shader instructions can be executed per clock cycle under certain parallelism conditions.
^ Unified shaders : Texture mapping units : Render output units : Ray accelerators : AI accelerators and Compute units (CU)

References