amdgpu is half of the device driver for AMD's GCN-based GPUs. There are two other "halfs" available, radeonsi, that is part of Mesa 3D and a proprietary half called AMDGPU-PRO. Originally the UMD radeonsi was written to work on top of the KMD radeon and AMDs proprietary UMD to work on top of fglrx.ko.
There is also RADV, which implements the Vulkan 1.0 specifications. RADV is strongly based on Intel's ANV driver but works on top of amdgpu (like radeonsi does, only that radeonsi implements OpenGL).[1]
History
edit- On January 9th, 2012 the first GCN-based product, the "Tahiti XT"-codenamed GPU (4313 million transistors organized as 2048:128:32) found on the Radeon HD 7970 graphics cards was released. Support for this card was added to the proprietary fglrx.ko as part of the AMD Catalyst for Linux driver package and later to /drm/radeon, serving as basis for the new UMD radeonsi in Mesa. Linux kernel 3.2 was released on January 4th, 2012 and 3.3 on March 18th, the same year.
- On March 22nd, 2013 the first GCN 2-based product, the "Bonaire XT"-codenamed GPU (2080 million transistors organized as 896:56:16) found on Radeon HD 7790 was released.
- On October 24th, 2013 the second GCN 2-based product, the "Hawaii XT"-codenamed GPU (6200 million transistors organized as 2816:176:64) was released.
- On October 7th, 2014 at the XDC 2014 Alex Deucher made the very fist announcement of AMD's new Linux support with a shared open-source kernel-mode driver[2] This was confirmed at the GDC 2015.
- In April 2015, the initial release of the new amdgpu-stack was announced on the dri-devel mailing list.[3]
- On August 30th, 2015 Linux kernel 4.2 including drivers/gpu/drm/amd/amdgpu was released; an own mailing list "amd-gfx" has been created for this development.
- DAL (Display Abstraction Layer) is part of amdgpu and was initially a huge set of patches (about 93,000 LoC) to the Linux kernel; but DAL has not been accepted into the Linux kernel; DAL is required to be distributed as part of AMD's new proprietary Linux driver "AMDGPU-Pro" and is being maintained and developed out-of-tree
- the DAL code was initially made available to the public in April 2015 on cgit.freedesktop.org/~agd5f
- On September 17th, 2015 at XDC there was another talk by Deucher and Zhou[4], the slides mention a new display component called "DAL" and a new new power component called "Powerplay" (though "powerplay" was replaced with "powertune")
- On 2016-02-11 Harry Wentland proposed to upstream DAL Enabling new DAL display driver for amdgpu on Carrizo and Tonga and was rejected
- On 2016-09-23 Harry Wentland presented DAL at the XDC2016: DAL presentation
- On 2016-12-08 Harry Wentland wrote a RFC regarding the acceptance of the DAL patch set
- The issue with out-of-tree code is that its developers need to rebase it from time to time and align it with current upstream. This consumes a lot of time, that might be used for fixing actual issues. To save time, DAL/DC hasn't been re-based from 4.4 to newer kernels. Though it seems that it has finally been moved to 4.14-devel to be mainlined into 4.15.
- On February 16th, 2016 Vulkan 1.0 was released Vulkan press-release
- In 2017-H1 Vega-GPUs will be available: hardware-wise "rasterisation and render output units" were changed and a much improved energy efficiency is expected from that.
Table
editVersion | Release date | browse | diff to prior | mails: drm-next pull request | Notes | Kernel version in Linux distributions: | |
---|---|---|---|---|---|---|---|
Stable | Rolling | ||||||
4.2 | 2015-08-30 | 4.2 | diff 4.2/4.1 | pull drm-next-4.2 | Basic support for GCN 3rd (Tonga, Fiji, Carrizo, Bristol Ridge), Experimental support for GCN 2nd (Bonaire, Hawaii, Kaveri, …), NO support for GCN 1st (Oland, Cape Verde, Pitcairn, Tahiti) |
Ubuntu 15.10 "Willy Werewolf", Fedora 23, … | Debian "Testing", Arch Linux, Ubuntu ppa, … |
4.3 | 2015-11-01 | 4.3 | diff 4.3/4.2 | pull drm-next-4.3 | Support for Fiji, Added drm/amd/scheduler | ||
4.4 LTS | 2016-01-10 | 4.4 | diff 4.4/4.3 | pull drm-next-4.4 | Support for Stoney, enable scheduler by default, | Ubuntu 16.04 LTS "Xenial Xerus" | |
4.5 | 2016-03-13 | 4.5 | diff 4.5/4.4 | pull drm-next-4.5 | Added drm/amd/powertune-modules for tonga, fiji, carrizo, stoney | Fedora 24, … | |
4.6 | 2016-05-15 | 4.6 | diff 4.6/4.5 | pull drm-next-4.6 | |||
4.7 | 2016-07-24 | 4.7 | diff 4.7/4.6 | pull drm-next-4.7 | Support for GCN 4th (Polaris 10, Polaris 11), current display stack on par with other ASICs; for advanced features DAL (Display Abstraction Layer) is required |
||
4.8 | 2016-09-25 | 4.8 | diff 4.8/4.7 | pull drm-next-4.8 | Over 20% of the patch is documentation updates, due to conversion of drm and media documentation from Docbook to the Sphinx doc format.[5] https://www.kernel.org/doc/html/latest/ |
Ubuntu 16.10 "Yakkety Yak", Fedora 25, Ubuntu 16.04.2 LTS with HWE (hardware enablement stack) | |
4.9 LTS | 2016-12-11 | 4.9 | diff 4.9/4.8 | pull drm-next-4.9 pull drm-next-4.9 |
Experimental support GCN 1st (Oland, Cape Verde, Pitcairn, Tahiti), SI support for amdgpu | Debian 9 "Stretch", SteamOS 31, … | |
4.10 | 2017-02-19 | 4.10 | diff 4.10/4.9 | 2016-Oct-27 2016-Nov-23 2016-Dec-08 |
Moving towards full support for GCN 1st explicit fencing mainlined lwn.net |
Ubuntu 17.04 "Zesty Zapus", … | |
4.11 | 2017-04-30 | 4.11 | diff 4.11/4.10 | 2017-Jan-27 2017-Feb-09 2017-Feb-16 2017-Feb-23 |
… (please look it up) | ||
4.12 | 2017-07-02 | 4.12 | diff 4.12/4.11 | Support for GCN 5th (Vega 10), | |||
4.13 | 2017-09-03 | 4.13 | diff 4.13/4.12 | Fedora 27, Ubuntu 17.10 "Artful Aardvark" | |||
4.14 LTS | 2017-11-12 | 4.14 | diff 4.14/4.13 | ||||
4.15 | 2018-01-28 | 4.15 | diff 4.15/4.14 | 2017-Sep-27 | The driver for the display controller was (finally) mainlined: drm/amd/display
|
Ubuntu 18.04 LTS "Bionic Beaver" | |
4.16 | 2018-04-01 | 4.16 | diff 4.16/4.15 | Fedora 28, … | |||
4.17 | 2018-06-03 | 4.17 | diff 4.17/4.16 | ||||
4.18 | 2018-08-12 | 4.18 | diff 4.18/4.17 | 2018-05-24 2018-05-31 |
Vega20 support, clock and power gating for VCN, … | Ubuntu 18.10 "Cosmic Cuttlefish", Fedora 29, … | |
4.19 LTS | 2018-10-22 | 4.19 | diff 4.19/4.18 | 2018-06-21 | add initial amdgpu documentation, add initial GPU scheduler documentation, add support for the JPEG engine on Video Core Next (VCN), … | ||
4.20 | 2018-12-23 | 4.20 | diff 4.20/4.19 | 2018-06-21 2018-09-14 |
|||
5.0 | 2019-03-03 | 5.0 | diff 5.0/4.20 | 2018-12-07 2012-12-12 2012-12-29 |
Ubuntu 19.04 "Disco Dingo", Fedora 30, … | ||
5.1 | 2019-05-05 | 5.1 | diff 5.1/5.0 | 2019-01-25 2019-02-01 2019-02-08 |
|||
5.2 | 2019-07-07 | 5.2 | diff 5.2/5.1 | ||||
5.3 | 2019-09-?? | ||||||
Legend: Old version, not maintained Old version, still maintained Latest version Latest preview version Future release |
1 SteamOS is based on a Debian stable release though a newer Linux kernel is later back-ported. Current version of SteamOS is at Linux kernel 4.1. It seems likely that SteamOS 3 will be based on Debian 9.
Other half
editamdgpu is only "half" of the graphics driver stack. Other halfs are Mesa and AMDGPU-PRO. AMDGPU-PRO Driver 17.30 (released 2017-07-27) is available for:
- RHEL 6.9 / CentOS 6.9 (Linux 2.6.32)
- RHEL 7.3 / CentOS 7.3 (Linux 3.10)
- SLED/SLES 12 SP2
- Ubuntu 16.04.2 (Linux 4.4, but also 4.8 HWE until 16.04.3 scheduled for August 2017)
Wild guesses
edit- phoronix ran some tests reported a comparison of "Linux 4.10.0" to the "current DRM-Next state" with "Mesa 17.1-dev". DRM-Next could mean
- Alex Deucher's: https://cgit.freedesktop.org/~agd5f/linux/log/?h=drm-next-4.11
- Dave Airlie's: https://cgit.freedesktop.org/~airlied/linux/log/?h=drm-next
- something else … sadly the author didn't bother to specify exactly what code he tested
- the exact code of "Mesa 17.1-dev" is also only know to the author…
- The tested hardware is a Sapphire Radeon RX 470 – a Radeon RX 480 was not tested – on a quad-code Xeon E3-1280 v5 (Skylake).
Deus Ex: Mankind Divided (2016-aug) – using the "Dawn Engine", reportedly based on the Glacier 2 game engine, which itself was used in Hitman: Absolution (2012) – scored significantly higher frame rates on the 4.11-drm-next code. Why? It's would be interesting to compare the two git-branches and see what kind of mechanics achieve twice the performance!
Explanations
editcode name | abbr. | version number | fab | concrete chips/dies | ||
---|---|---|---|---|---|---|
"southern islands" | si | GCN 1 | GCN1st | GCN 1.0 | 28 nm | Oland, Cape Verde, Pitcairn, Tahiti |
"sea islands" | ci | GCN 2 | GCN2nd | GCN 1.1 | Bonaire, Hawaii; cik refers to the GPU on some of the APUs | |
"volcanic islands" | vi | GCN 3 | GCN3rd | GCN 1.2 | Tonga, Fiji; uses GCA (Graphics and Compute Array) version 8.0 | |
"arctic islands" | ai | GCN 4 | GCN4th | GCN 1.3 | 14 nm | Polaris 10/11/12; uses GCA (Graphics and Compute Array) version 8.0 |
"vega" | vega | GCN 5 | GCN5th | GCN 2.0 | Vega 10/11 |
There are three different Device Dependent X (DDX)-drivers available:
- xf86-video-ati = the old proprietary DDX driver; works on top of fglrx.ko in parallel with the proprietary OpenGL driver.
- xf86-video-radeon = the FOSS DDX driver in Mesa; works on top of /drm/radeon
- xf86-video-amdgpu = the FOSS DDX driver by AMD; works in top of /drm/amd/amdgpu in parallel with proprietary OpenGL driver and with Mesa; uses Glamor!
The interface libraries for amdgpu are libdrm_generic and libdrm_amdgpu, cf. https://lwn.net/Articles/654542/.
cf. Free_and_open-source_graphics_device_driver#ATI.2FAMD, Graphics Core Next, commons:Category:Diagrams illustrating AMD technology
- Note: AMD publishes 3D shader and command queue documentation, AMD does do NOT publish register docs for recent GPUs. Information:
- https://fail0verflow.com/media/33c3-slides/index.html#/74
- https://www.x.org/wiki/RadeonFeature/#index5h2
- https://wiki.gentoo.org/wiki/AMDGPU
- drivers/gpu/drm/amd/include/asic_reg/
- bif = Bus InterFace (implements i.a. the PCI Express endpoint)
- dce = Display Controller Engine (this actually received an own brand-name: AMD Eyefinity)
- gca = Graphics and Compute Array
- gmc = Graphics Memory Controller (implements i.a. the GDDR5 SDRAM/HBM controller)
- oss = Operating System Services
- smu = System Management Unit (includes a LatticeMico32, fulfills system management and power management tasks)
- uvd = Unified Video Decoder
- vce = Video Coding Engine
For more statistics see e.g. heise.de and of course the man page for git.
Commands are sent to the GPU by putting them in rings:
- Graphics ring
- Compute rings
- DMA rings (seem to be only GCN 1.1 aka GCN 2nd aka Bonaire, Hawaii and newer)
Commands are processed by the GPU Command Processor. It contains multiple sub-units (ME (Micro Engine), PFP (Prefetch Parser), CE (Constant Engine), DE (Dispatch Engine)), each of which is a custom ‘F32’ CPU running microcode firmware. Rings can call out to Indirect Buffers (IBs) with more commands
GCN 1:
All resource descriptors (sometimes called “fetch constants” on previous hardware) are read from memory instead of registers. In order to improve performance, the CP block adds a new constant engine. The constant engine (CE) runs in parallel to the 3D engine, and allows constants to be written to memory ahead of the main command stream.
Updating Shader Resource Descriptors (SRDs) using the CPU would be too slow. The CP provides a constant update engine to accelerate the process.
PM4 is the packet API used to program the GPU to perform a variety of tasks. The driver does not write directly to the GPU registers to carry out drawing operations on the screen. Instead, it prepares data in the format of "PM4 Command Packets" in either system or video (a.k.a. local) memory, and lets the Micro Engine to do the rest of the job.
There are two CP engines on SI: the Constant Engine (CE) and the Drawing Engine (DE). Previous ASICs only had a DE (previously referred to as the Micro-Engine or ME). Certain packets are only allowed on the DE or the CE. Packets can be executed in the DE via the ring or via an INDIRECT_BUFFER packet. Packets can only be executed on the CE by using the INDIRECT_BUFFER_CONST packet.
- Draw Engine (DE): The standard graphics engine is now referred to as the Draw Engine. Most PM4 commands continue to be submitted to the DE command buffer.
- Constant Engine (CE): The constant engine uses a second, separate command buffer to control constant uploads. The engine runs in parallel with the draw engine, allowing constant updates to get sufficiently ahead of the draws/dispatches that will use them. Additionally, CP has 64KiB of on-chip RAM (CE RAM) that acts as a staging buffer for constant updates. Shaders cannot read directly from the CE RAM.
The 64KiB is carved up between the 3 rings, with ring-0 (gfx) having 32KB. The driver is responsible for further subdividing the partitions to store an on-chip copy of the most up-to-date copy of every SRD.
There are two CP engines on GCN 1.0 (SI, Southern Island): the Constant Engine (CE) and the Drawing Engine (DE). Previous ASICs only had a DE (previously referred to as the Micro-Engine or ME).
The purpose of this packet is to provide a generic and flexible way for the CP to write n Dwords of data to any destination to which it has access. As applicable, the writes can be sent from the CE, PFP, ME or DE (Dispatch Engine). The CE (and PFP) are limited to the GRBM (Graphics Register Backbone Manager) and MC (memory controller?) as destinations.
Note: The split between SRBM and GRBM is mostly between "3D engine" and "everything else" – register writes to the 3D engine need to be synchronized with the data flowing through the engine so the register logic is *really* complicated. The rest of the registers don't need to be pipelined and so are managed by a separate block. Most graphics/3D registers sit behind a FIFO, while other (display/asic setup/config) registers do not.
CB | Color Block | Color buffer |
CP | Command Processor | aka Graphics Command Processor |
DB | Depth Block | Depth buffer |
EE | Event Engine | ? |
GRBM | Graphics Register Block Manager | Registers (0x8000-0x2fffc)? |
ME | Micro Engine | (the things that run the CP/PFP microcode) |
PA | Primitive Assembler | Scissors, Cliprects, Point sprites |
SE | Shader Engine | What Compute Units (CUs) are grouped into. Both Hawaii (44 CUs) and Fiji (64 CUs) have 4. Other have 2 or so. |
SPI | Shader Processor Interpolator | Semantic mapping, interpolators |
SQ | Sequencer / Shader | Shader management, exports, register alloc |
SRBM | System Register Block Manager | Registers (0x0000-0x7ffc)? |
SX | Shader Export | Output mapping, output buffers |
TA | Texture Addresser | ? |
VGT | Vertex Grouper Tessellator | Everthing related to vertex setup, viewport transformation, etc. |
Hardware
editNote: The following tables refer always to the most current stable Linux kernel version, i.e. support for Polaris is available only since Linux kernel 4.7 and not present in earlier versions!
The following table shows features of AMD/ATI's GPUs (see also: List of AMD graphics processing units).
Name of GPU series | Wonder | Mach | 3D Rage | Rage Pro | Rage 128 | R100 | R200 | R300 | R400 | R500 | R600 | RV670 | R700 | Evergreen | Northern Islands |
Southern Islands |
Sea Islands |
Volcanic Islands |
Arctic Islands/Polaris |
Vega | Navi 1x | Navi 2x | Navi 3x | |||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Released | 1986 | 1991 | Apr 1996 |
Mar 1997 |
Aug 1998 |
Apr 2000 |
Aug 2001 |
Sep 2002 |
May 2004 |
Oct 2005 |
May 2007 |
Nov 2007 |
Jun 2008 |
Sep 2009 |
Oct 2010 |
Jan 2012 |
Sep 2013 |
Jun 2015 |
Jun 2016, Apr 2017, Aug 2019 | Jun 2017, Feb 2019 | Jul 2019 |
Nov 2020 |
Dec 2022 | |||
Marketing Name | Wonder | Mach | 3D Rage |
Rage Pro |
Rage 128 |
Radeon 7000 |
Radeon 8000 |
Radeon 9000 |
Radeon X700/X800 |
Radeon X1000 |
Radeon HD 2000 |
Radeon HD 3000 |
Radeon HD 4000 |
Radeon HD 5000 |
Radeon HD 6000 |
Radeon HD 7000 |
Radeon 200 |
Radeon 300 |
Radeon 400/500/600 |
Radeon RX Vega, Radeon VII |
Radeon RX 5000 |
Radeon RX 6000 |
Radeon RX 7000 | |||
AMD support | ||||||||||||||||||||||||||
Kind | 2D | 3D | ||||||||||||||||||||||||
Instruction set architecture | Not publicly known | TeraScale instruction set | GCN instruction set | RDNA instruction set | ||||||||||||||||||||||
Microarchitecture | TeraScale 1 (VLIW) |
TeraScale 2 (VLIW5) |
|
GCN 1st gen |
GCN 2nd gen |
GCN 3rd gen |
GCN 4th gen |
GCN 5th gen |
RDNA | RDNA 2 | RDNA 3 | |||||||||||||||
Type | Fixed pipeline[a] | Programmable pixel & vertex pipelines | Unified shader model | |||||||||||||||||||||||
Direct3D | — | 5.0 | 6.0 | 7.0 | 8.1 | 9.0 11 (9_2) |
9.0b 11 (9_2) |
9.0c 11 (9_3) |
10.0 11 (10_0) |
10.1 11 (10_1) |
11 (11_0) | 11 (11_1) 12 (11_1) |
11 (12_0) 12 (12_0) |
11 (12_1) 12 (12_1) |
11 (12_1) 12 (12_2) | |||||||||||
Shader model | — | 1.4 | 2.0+ | 2.0b | 3.0 | 4.0 | 4.1 | 5.0 | 5.1 | 5.1 6.5 |
6.7 | |||||||||||||||
OpenGL | — | 1.1 | 1.2 | 1.3 | 2.1[b][9] | 3.3 | 4.5[10][11][12][c] | 4.6 | ||||||||||||||||||
Vulkan | — | 1.0 | 1.2 | 1.3 | ||||||||||||||||||||||
OpenCL | — | Close to Metal | 1.1 (not supported by Mesa) | 1.2+ (on Linux: 1.1+ (no Image support on clover, with by rustiCL) with Mesa, 1.2+ on GCN 1.Gen) | 2.0+ (Adrenalin driver on Win7+) (on Linux ROCM, Mesa 1.2+ (no Image support in clover, but in rustiCL with Mesa, 2.0+ and 3.0 with AMD drivers or AMD ROCm), 5th gen: 2.2 win 10+ and Linux RocM 5.0+ |
2.2+ and 3.0 windows 8.1+ and Linux ROCM 5.0+ (Mesa rustiCL 1.2+ and 3.0 (2.1+ and 2.2+ wip))[13][14][15] | ||||||||||||||||||||
HSA / ROCm | — | ? | ||||||||||||||||||||||||
Video decoding ASIC | — | Avivo/UVD | UVD+ | UVD 2 | UVD 2.2 | UVD 3 | UVD 4 | UVD 4.2 | UVD 5.0 or 6.0 | UVD 6.3 | UVD 7 [16][d] | VCN 2.0 [16][d] | VCN 3.0 [17] | VCN 4.0 | ||||||||||||
Video encoding ASIC | — | VCE 1.0 | VCE 2.0 | VCE 3.0 or 3.1 | VCE 3.4 | VCE 4.0 [16][d] | ||||||||||||||||||||
Fluid Motion [e] | ? | |||||||||||||||||||||||||
Power saving | ? | PowerPlay | PowerTune | PowerTune & ZeroCore Power | ? | |||||||||||||||||||||
TrueAudio | — | Via dedicated DSP | Via shaders | |||||||||||||||||||||||
FreeSync | — | 1 2 | ||||||||||||||||||||||||
HDCP[f] | ? | 1.4 | 2.2 | 2.3 [18] | ||||||||||||||||||||||
PlayReady[f] | — | 3.0 | 3.0 | |||||||||||||||||||||||
Supported displays[g] | 1–2 | 2 | 2–6 | ? | ||||||||||||||||||||||
Max. resolution | ? | 2–6 × 2560×1600 |
2–6 × 4096×2160 @ 30 Hz |
2–6 × 5120×2880 @ 60 Hz |
3 × 7680×4320 @ 60 Hz [19] |
7680×4320 @ 60 Hz PowerColor |
7680x4320
@165 HZ | |||||||||||||||||||
/drm/radeon [h]
|
— | |||||||||||||||||||||||||
/drm/amdgpu [h]
|
— | Experimental [20] | Optional [21] |
- ^ The Radeon 100 Series has programmable pixel shaders, but do not fully comply with DirectX 8 or Pixel Shader 1.0. See article on R100's pixel shaders.
- ^ R300, R400 and R500 based cards do not fully comply with OpenGL 2+ as the hardware does not support all types of non-power of two (NPOT) textures.
- ^ OpenGL 4+ compliance requires supporting FP64 shaders and these are emulated on some TeraScale chips using 32-bit hardware.
- ^ a b c The UVD and VCE were replaced by the Video Core Next (VCN) ASIC in the Raven Ridge APU implementation of Vega.
- ^ Video processing for video frame rate interpolation technique. In Windows it works as a DirectShow filter in your player. In Linux, there is no support on the part of drivers and / or community.
- ^ a b To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
- ^ More displays may be supported with native DisplayPort connections, or splitting the maximum resolution between multiple monitors with active converters.
- ^ a b DRM (Direct Rendering Manager) is a component of the Linux kernel. AMDgpu is the Linux kernel module. Support in this table refers to the most current version.
The following table shows features of AMD's processors with 3D graphics, including APUs (see also: List of AMD processors with 3D graphics).
Platform | High, standard and low power | Low and ultra-low power | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Codename | Server | Basic | Toronto | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Micro | Kyoto | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Desktop | Performance | Raphael | Phoenix | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Mainstream | Llano | Trinity | Richland | Kaveri | Kaveri Refresh (Godavari) | Carrizo | Bristol Ridge | Raven Ridge | Picasso | Renoir | Cezanne | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Entry | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Basic | Kabini | Dalí | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Mobile | Performance | Renoir | Cezanne | Rembrandt | Dragon Range | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Mainstream | Llano | Trinity | Richland | Kaveri | Carrizo | Bristol Ridge | Raven Ridge | Picasso | Renoir Lucienne |
Cezanne Barceló |
Phoenix | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Entry | Dalí | Mendocino | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Basic | Desna, Ontario, Zacate | Kabini, Temash | Beema, Mullins | Carrizo-L | Stoney Ridge | Pollock | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Embedded | Trinity | Bald Eagle | Merlin Falcon, Brown Falcon |
Great Horned Owl | Grey Hawk | Ontario, Zacate | Kabini | Steppe Eagle, Crowned Eagle, LX-Family |
Prairie Falcon | Banded Kestrel | River Hawk | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Released | Aug 2011 | Oct 2012 | Jun 2013 | Jan 2014 | 2015 | Jun 2015 | Jun 2016 | Oct 2017 | Jan 2019 | Mar 2020 | Jan 2021 | Jan 2022 | Sep 2022 | Jan 2023 | Jan 2011 | May 2013 | Apr 2014 | May 2015 | Feb 2016 | Apr 2019 | Jul 2020 | Jun 2022 | Nov 2022 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
CPU microarchitecture | K10 | Piledriver | Steamroller | Excavator | "Excavator+"[22] | Zen | Zen+ | Zen 2 | Zen 3 | Zen 3+ | Zen 4 | Bobcat | Jaguar | Puma | Puma+[23] | "Excavator+" | Zen | Zen+ | "Zen 2+" | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
ISA | x86-64 v1 | x86-64 v2 | x86-64 v3 | x86-64 v4 | x86-64 v1 | x86-64 v2 | x86-64 v3 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Socket | Desktop | Performance | — | AM5 | — | — | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Mainstream | — | AM4 | — | — | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Entry | FM1 | FM2 | FM2+ | FM2+[a], AM4 | AM4 | — | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Basic | — | — | AM1 | — | FP5 | — | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Other | FS1 | FS1+, FP2 | FP3 | FP4 | FP5 | FP6 | FP7 | FL1 | FP7 FP7r2 FP8 |
? | FT1 | FT3 | FT3b | FP4 | FP5 | FT5 | FP5 | FT6 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
PCI Express version | 2.0 | 3.0 | 4.0 | 5.0 | 4.0 | 2.0 | 3.0 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
CXL | — | — | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Fab. (nm) | GF 32SHP (HKMG SOI) |
GF 28SHP (HKMG bulk) |
GF 14LPP (FinFET bulk) |
GF 12LP (FinFET bulk) |
TSMC N7 (FinFET bulk) |
TSMC N6 (FinFET bulk) |
CCD: TSMC N5 (FinFET bulk) cIOD: TSMC N6 (FinFET bulk) |
TSMC 4nm (FinFET bulk) |
TSMC N40 (bulk) |
TSMC N28 (HKMG bulk) |
GF 28SHP (HKMG bulk) |
GF 14LPP (FinFET bulk) |
GF 12LP (FinFET bulk) |
TSMC N6 (FinFET bulk) | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Die area (mm2) | 228 | 246 | 245 | 245 | 250 | 210[24] | 156 | 180 | 210 | CCD: (2x) 70 cIOD: 122 |
178 | 75 (+ 28 FCH) | 107 | ? | 125 | 149 | ~100 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Min TDP (W) | 35 | 17 | 12 | 10 | 15 | 65 | 35 | 4.5 | 4 | 3.95 | 10 | 6 | 12 | 8 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Max APU TDP (W) | 100 | 95 | 65 | 45 | 170 | 54 | 18 | 25 | 6 | 54 | 15 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Max stock APU base clock (GHz) | 3 | 3.8 | 4.1 | 4.1 | 3.7 | 3.8 | 3.6 | 3.7 | 3.8 | 4.0 | 3.3 | 4.7 | 4.3 | 1.75 | 2.2 | 2 | 2.2 | 3.2 | 2.6 | 1.2 | 3.35 | 2.8 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Max APUs per node[b] | 1 | 1 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Max core dies per CPU | 1 | 2 | 1 | 1 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Max CCX per core die | 1 | 2 | 1 | 1 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Max cores per CCX | 4 | 8 | 2 | 4 | 2 | 4 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Max CPU[c] cores per APU | 4 | 8 | 16 | 8 | 2 | 4 | 2 | 4 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Max threads per CPU core | 1 | 2 | 1 | 2 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Integer pipeline structure | 3+3 | 2+2 | 4+2 | 4+2+1 | 1+3+3+1+2 | 1+1+1+1 | 2+2 | 4+2 | 4+2+1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
IOMMU[d] | — | v2 | v1 | v2 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
BMI1, AES-NI, CLMUL, and F16C | — | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
MOVBE | — | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
AVIC, BMI2, RDRAND, and MWAITX/MONITORX | — | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
SME[e], TSME[e], ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing | — | — | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
GMET, WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT | — | — | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
MPK, VAES | — | — | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
SGX | — | — | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
FPUs per core | 1 | 0.5 | 1 | 1 | 0.5 | 1 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Pipes per FPU | 2 | 2 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
FPU pipe width | 128-bit | 256-bit | 80-bit | 128-bit | 256-bit | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
CPU instruction set SIMD level | SSE4a[f] | AVX | AVX2 | AVX-512 | SSSE3 | AVX | AVX2 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3DNow! | 3DNow!+ | — | — | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
PREFETCH/PREFETCHW | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
GFNI | — | — | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
AMX | — | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
FMA4, LWP, TBM, and XOP | — | — | — | — | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
FMA3 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
AMD XDNA | — | — | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
L1 data cache per core (KiB) | 64 | 16 | 32 | 32 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
L1 data cache associativity (ways) | 2 | 4 | 8 | 8 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
L1 instruction caches per core | 1 | 0.5 | 1 | 1 | 0.5 | 1 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Max APU total L1 instruction cache (KiB) | 256 | 128 | 192 | 256 | 512 | 256 | 64 | 128 | 96 | 128 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
L1 instruction cache associativity (ways) | 2 | 3 | 4 | 8 | 2 | 3 | 4 | 8 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
L2 caches per core | 1 | 0.5 | 1 | 1 | 0.5 | 1 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Max APU total L2 cache (MiB) | 4 | 2 | 4 | 16 | 1 | 2 | 1 | 2 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
L2 cache associativity (ways) | 16 | 8 | 16 | 8 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Max on--die L3 cache per CCX (MiB) | — | 4 | 16 | 32 | — | 4 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Max 3D V-Cache per CCD (MiB) | — | 64 | — | — | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Max total in-CCD L3 cache per APU (MiB) | 4 | 8 | 16 | 64 | 4 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Max. total 3D V-Cache per APU (MiB) | — | 64 | — | — | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Max. board L3 cache per APU (MiB) | — | — | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Max total L3 cache per APU (MiB) | 4 | 8 | 16 | 128 | 4 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
APU L3 cache associativity (ways) | 16 | 16 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
L3 cache scheme | Victim | Victim | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Max. L4 cache | — | — | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Max stock DRAM support | DDR3-1866 | DDR3-2133 | DDR3-2133, DDR4-2400 | DDR4-2400 | DDR4-2933 | DDR4-3200, LPDDR4-4266 | DDR5-4800, LPDDR5-6400 | DDR5-5200 | DDR5-5600, LPDDR5x-7500 | DDR3L-1333 | DDR3L-1600 | DDR3L-1866 | DDR3-1866, DDR4-2400 | DDR4-2400 | DDR4-1600 | DDR4-3200 | LPDDR5-5500 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Max DRAM channels per APU | 2 | 1 | 2 | 1 | 2 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Max stock DRAM bandwidth (GB/s) per APU | 29.866 | 34.132 | 38.400 | 46.932 | 68.256 | 102.400 | 83.200 | 120.000 | 10.666 | 12.800 | 14.933 | 19.200 | 38.400 | 12.800 | 51.200 | 88.000 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
GPU microarchitecture | TeraScale 2 (VLIW5) | TeraScale 3 (VLIW4) | GCN 2nd gen | GCN 3rd gen | GCN 5th gen[25] | RDNA 2 | RDNA 3 | TeraScale 2 (VLIW5) | GCN 2nd gen | GCN 3rd gen[25] | GCN 5th gen | RDNA 2 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
GPU instruction set | TeraScale instruction set | GCN instruction set | RDNA instruction set | TeraScale instruction set | GCN instruction set | RDNA instruction set | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Max stock GPU base clock (MHz) | 600 | 800 | 844 | 866 | 1108 | 1250 | 1400 | 2100 | 2400 | 400 | 538 | 600 | ? | 847 | 900 | 1200 | 600 | 1300 | 1900 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Max stock GPU base GFLOPS[g] | 480 | 614.4 | 648.1 | 886.7 | 1134.5 | 1760 | 1971.2 | 2150.4 | 3686.4 | 102.4 | 86 | ? | ? | ? | 345.6 | 460.8 | 230.4 | 1331.2 | 486.4 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3D engine[h] | Up to 400:20:8 | Up to 384:24:6 | Up to 512:32:8 | Up to 704:44:16[26] | Up to 512:32:8 | 768:48:8 | 128:8:4 | 80:8:4 | 128:8:4 | Up to 192:12:8 | Up to 192:12:4 | 192:12:4 | Up to 512:?:? | 128:?:? | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
IOMMUv1 | IOMMUv2 | IOMMUv1 | ? | IOMMUv2 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Video decoder | UVD 3.0 | UVD 4.2 | UVD 6.0 | VCN 1.0[27] | VCN 2.1[28] | VCN 2.2[28] | VCN 3.1 | ? | UVD 3.0 | UVD 4.0 | UVD 4.2 | UVD 6.0 | UVD 6.3 | VCN 1.0 | VCN 3.1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Video encoder | — | VCE 1.0 | VCE 2.0 | VCE 3.1 | — | VCE 2.0 | VCE 3.1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
AMD Fluid Motion | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
GPU power saving | PowerPlay | PowerTune | PowerPlay | PowerTune[29] | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
TrueAudio | — | [30] | ? | — | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
FreeSync | 1 2 |
1 2 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
HDCP[i] | ? | 1.4 | 2.2 | 2.3 | ? | 1.4 | 2.2 | 2.3 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
PlayReady[i] | — | 3.0 not yet | — | 3.0 not yet | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Supported displays[j] | 2–3 | 2–4 | 3 | 3 (desktop) 4 (mobile, embedded) |
4 | 2 | 3 | 4 | 4 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
/drm/radeon [k][32][33] |
— | — | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
/drm/amdgpu [k][34] |
— | [35] | — | [35] |
- ^ For FM2+ Excavator models: A8-7680, A6-7480 & Athlon X4 845.
- ^ A PC would be one node.
- ^ An APU combines a CPU and a GPU. Both have cores.
- ^ Requires firmware support.
- ^ a b Requires firmware support.
- ^ No SSE4. No SSSE3.
- ^ Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
- ^ Unified shaders : texture mapping units : render output units
- ^ a b To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
- ^ To feed more than two displays, the additional panels must have native DisplayPort support.[31] Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.
- ^ a b DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version.
- ^ "RADV conforms to Vulkan 1.0". 2017-10-04.
- ^ "Alex Deucher - AMD's New Unified Open Source Driver". 2014-10-07.
- ^ "Initial amdgpu driver release". 2015-04-20.
- ^ "update on amdgpu and future". 2015-09-17.
- ^ Torvalds, Linus (2016-08-07). "Linux 4.8-rc1".
- ^ "No support for GCN 1.0 hardware, e.g. Tahiti XT". 2018-01-29.
- ^ "AMD Radeon HD 6900 (AMD Cayman) series graphics cards". HWlab. hw-lab.com. December 19, 2010. Archived from the original on August 23, 2022. Retrieved August 23, 2022.
New VLIW4 architecture of stream processors allowed to save area of each SIMD by 10%, while performing the same compared to previous VLIW5 architecture
- ^ "GPU Specs Database". TechPowerUp. Retrieved August 23, 2022.
- ^ "NPOT Texture (OpenGL Wiki)". Khronos Group. Retrieved February 10, 2021.
- ^ "AMD Radeon Software Crimson Edition Beta". AMD. Retrieved 2018-04-20.
- ^ "Mesamatrix". mesamatrix.net. Retrieved 2018-04-22.
- ^ "RadeonFeature". X.Org Foundation. Retrieved 2018-04-20.
- ^ "AMD Radeon RX 6800 XT Specs". TechPowerUp. Retrieved January 1, 2021.
- ^ "AMD Launches The Radeon PRO W7500/W7600 RDNA3 GPUs". Phoronix. 3 August 2023. Retrieved 4 September 2023.
- ^ "AMD Radeon Pro 5600M Grafikkarte". TopCPU.net (in German). Retrieved 4 September 2023.
- ^ a b c Killian, Zak (March 22, 2017). "AMD publishes patches for Vega support on Linux". Tech Report. Retrieved March 23, 2017.
- ^ Larabel, Michael (September 15, 2020). "AMD Radeon Navi 2 / VCN 3.0 Supports AV1 Video Decoding". Phoronix. Retrieved January 1, 2021.
- ^ Edmonds, Rich (February 4, 2022). "ASUS Dual RX 6600 GPU review: Rock-solid 1080p gaming with impressive thermals". Windows Central. Retrieved November 1, 2022.
- ^ "Radeon's next-generation Vega architecture" (PDF). Radeon Technologies Group (AMD). Archived from the original (PDF) on September 6, 2018. Retrieved June 13, 2017.
- ^ Larabel, Michael (December 7, 2016). "The Best Features of the Linux 4.9 Kernel". Phoronix. Retrieved December 7, 2016.
- ^ "AMDGPU". Retrieved December 29, 2023.
- ^ "AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks". 31 May 2016. Retrieved 3 January 2020.
- ^ "AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015" (Press release). 20 November 2014. Retrieved 16 February 2015.
- ^ "The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List". TechARP.com. Retrieved 13 December 2017.
- ^ a b "AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". VideoCardz.com. Retrieved 6 June 2017.
- ^ Cutress, Ian (1 February 2018). "Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm". Anandtech. Retrieved 7 February 2018.
- ^ Larabel, Michael (17 November 2017). "Radeon VCN Encode Support Lands in Mesa 17.4 Git". Phoronix. Retrieved 20 November 2017.
- ^ a b "AMD Ryzen 5000G 'Cezanne' APU Gets First High-Res Die Shots, 10.7 Billion Transistors In A 180mm2 Package". wccftech. Aug 12, 2021. Retrieved August 25, 2021.
- ^ Tony Chen; Jason Greaves, "AMD's Graphics Core Next (GCN) Architecture" (PDF), AMD, retrieved 13 August 2016
- ^ "A technical look at AMD's Kaveri architecture". Semi Accurate. Retrieved 6 July 2014.
- ^ "How do I connect three or More Monitors to an AMD Radeon™ HD 5000, HD 6000, and HD 7000 Series Graphics Card?". AMD. Retrieved 8 December 2014.
- ^ Airlie, David (26 November 2009). "DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33". Retrieved 16 January 2016.
- ^ "Radeon feature matrix". freedesktop.org. Retrieved 10 January 2016.
- ^ Deucher, Alexander (16 September 2015). "XDC2015: AMDGPU" (PDF). Retrieved 16 January 2016.
- ^ a b Michel Dänzer (17 November 2016). "[ANNOUNCE] xf86-video-amdgpu 1.2.0". lists.x.org.