User:Vitaltrust/sandbox

This is the user sandbox of Vitaltrust. A user sandbox is a subpage of the user's user page. It serves as a testing spot and page development space for the user and is not an encyclopedia article. Create or edit your own sandbox here.

Other sandboxes: Main sandbox | Template sandbox

Finished writing a draft article? Are you ready to request review of it by an experienced editor for possible inclusion in Wikipedia? Submit your draft for review!

Request of explanation: why Q-IV is the least sensitive quadrant?

Can anybody explain why the fourth quadrant requires the most current to trigger the device? As a circuit designer, I always find this both in literature and on the datasheets, but I've never found an explanation of what causes this behaviour at the semiconductor level. --Vitaltrust (talk) 15:48, 29 October 2011 (UTC)

Yeah, that's what my original {{clarify}} was really about. So, I've restored the {{clarify}} and added others where Q-IV and Q-I sensitivity is addressed. I understood that Q-IV is the least sensitive and the generic definition of "less sensitive" (which is why I edited that from the article) but why Q-IV is the least sensitive (and Q-I is most sensitive) isn't explained in the article.

Okay, here's an attempt to explain it. What's important to remember is that the two cross-connected transistors in a thyristor are not designed for high beta; rather, they are usually optimized for things like standoff voltage. This is mostly carried by the inner N layer, which is very lightly doped (N−); the N layers adjacent to the electrodes are more heavily doped (N+).

For a 4-layer thyristor to operate, the product of the current gains of the two transistors must exceed 1. Note that one of the betas may be and often is less than 1! Only the product matters. The important thing to remember is that these are very low-beta transistors. Just because I talk about a set of 3 layers making a transistor does not mean there's current gain.

First, start with the basic quadrant I and II operation, where the main transistors are NPN on top and PNP below.

In quadrant 1, the gate is shoving current straight into the base of the NPN transistor, making it easy to trigger.

In quadrant 2, the base does not trigger the NPNP transistor stack directly, but rather the it is the emitter of a secondary NPN, with A1 as the base, and the inner N− layer being the collector. When the collector current is high enough, this turns on the PNP of the main thyristor stack and things start to happen. But this first transistor has less than unity current gain, requiring more gate current to fire up the thyristor stack. Despite having less than unity gain, it's a separate transistor, and some work can be put into optimizing its operation.

In quadrant 3, the main stack is no longer NPN on top, but rather PNPN, with the top A1 conducting through its P layer, and the bottom A2 conducting through its N+ layer. Again, these transistors have a combined current gain barely more than 1.

Despite this change, triggering is almost the same as in quadrant 2. The same secondary NPN is used to pull current out of the the N− base of the main PNP, turning on the stack; it's only the location of the main NPN that differs.

Now, quadrant 4. Here's where things get interesting. Like quadrant 1, the gate current goes straight into the base of a "main" NPN. However, this NPN is no longer on the main current path! Because the thyristor is flipped, the active "main" NPN is now on the other side, adjacent to A2. Rather, this transistor, which is designed and optimized to be a "main" transistor, has to be turned on soley by the gate current, with no help from positive feedback, until it pulls enough current out of the main PNP to start the thyristor stack.

You may recall that the beta of a silicon transistor is maximized for a "medium" collector current. At low currents, the beta is lower than normal. And the gate current, spread out across the huge main transistor area, is definitely operating in that region. (Quadrant 1 suffers from the same problem, but the positive feedback quickly starts to kick in and solve it for us.)

So the upshot is that Quadrant 1 triggers the internal SCR directly. Quadrants 2 and 3 do so via an auxiliary NPN, which is a pretty bad NPN, but at least it's small and not too hard to turn on. But quadrant 4 has to turn on a large main NPN to turn on the internal SCR, which takes a lot of current.

Does that make sense? 71.41.210.146 (talk) 06:50, 15 April 2012 (UTC)

As a follow-up, let me see if I can draw a TRIAC as four transistors using ASCII art.

First of all, a 5-layer DIAC is basically

     A1
     |
  +--+--+
  |     /
  |    n (E)
  +---p
  |    n (C)
  \     \
   p    |
    n---+
   p    |
  /     /
  |    n (C)
  +---p
  |    n (E)
  |     \
  +--+--+
     |
     A2

Now, let me add the gate, which is a secondary NPN in parallel with A1's:

     A1     G
     |      |
  +--+--+ +-+-+
  |     / |   /
  |    n  |  n (E)
  +---p---+-p      Q2 Q4
  |    n     n (C)
  \     \     \
   p    |     |
    n---+-----+    Q1
   p    |
  /     /
  |    n (C)
  +---p            Q3
  |    n (E)
  |     \
  +--+--+
     |
     A2

In quadrants 1 and 2, the main thyristor is Q1 and Q2. In quadrants 3 and 4, the main thyristor is Q1 and Q3.
In quadrants 1 and 4, the gate current turns on Q2, by injecting holes directly into its base. In quadrants 2 and 3, the gate current turns on Q4 by pulling its emitter down while A1 provides the base current.
Either way, the result is base current pulled out of Q1's base, and the thyristor turns on.
When understanding the gate action, it's important to recognize that there's significant resistance in the P layer, which divide all the transistors into lots of little transistors connected in parallel. Even through the circuit shows A1 and G connected by it, they are not necessarily at the same voltage. Some current flows (the dotted line in Figure 3), but enough flows across Q2's B-E junction to turn it on.
Likewise, in quadrants 2 and 3, the gate can pull Q4's emitter below the base (held high by A1) to turn it on.
The hardest thing is quadrant 4 triggering, where the gate has to turn on Q2, but there's no voltage on the collector to help.

71.41.210.146 (talk) 16:39, 15 April 2012 (UTC)

Overall, I largely agree with your explanation. I agree that the main reason is probably that you have to drag current out of the "central" N-layer, even acting against the voltage potential (in quadrant IV MT2 is'-'), using a structure that is farther from the main current path than quadrant III (where actually the triggering process is similar). However, it is better to provide some references before putting all this into the article. Do you have any sources? —Vitaltrust (talk) 21:27, 22 April 2012 (UTC)

Unfortunately, no I don't have sources; I worked it out from first principles. And after thinking hard about what you wrote, I realize that my explanation on Q-IV is incomplete, and there's a far more obvious effect causing the difference.

In Q-I operation, the main current path is A1-NPNP-A2(+). The two NP junctions have one Vbe drop across them (nominally 0.7V, but actually much less when in the off state, as the current is negligible), and the main PN junction bears the brunt of the standoff voltage. This is the collector-base junction of the two transistors. The gate connects to the base of the initial NPN, and when it is pulled high, the transistor is operating in the "active" region, with significant collector-emitter voltage, and thus high beta.

In Q-IV, the main current path is A1-PNPN-A2(−). The two PN junctions have Vbe forward drops across them, and the NP junction is the collector-base junction of the two transistors, and holds the standoff voltage.

The gate connects to the base of a separate NPN, whose emitter is also A1, and whose collector is the base of the PNP. When you put current across this transistor's base-emitter junction (by raising the gate one Vbe above A1), the collector voltage is one diode drop less than A1. (As mentioned before, this is a lot less than 0.7V, in fact almost 0V, because the forward current is almost zero.)

This is deep in the saturation region, where a transistor's effective beta is greatly reduced. The main thyristor is triggered identicially to Q-III, but with the collector current of this transistor rather than the gate current directly. It never was a high-beta transistor to start with, and now it's trying to operate with a slightly *reversed* Vce, reducing it to something less than unity. Thus, the Q-IV triggering current is more than the Q-III triggering current.

Does that make sense? 71.41.210.146 (talk) 23:35, 25 April 2012 (UTC)

Well, let me put my comments directly into the text you wrote above and put there my remarks.

In Q-I operation, the main current path is A1-NPNP-A2(+). Y The two NP junctions have one Vbe drop across them (nominally 0.7V, but actually much less when in the off state, as the current is negligible), and the main PN junction bears the brunt of the standoff voltage. This is the collector-base junction of the two transistors. YI agree. Since both the NPN (adjoining MT1 and GATE) and the PNP (adjoining MT2) must be off, the base of the PNP must be higher than VMT2-0.7V, much of the voltage across the whole device is borne by the junction between the collector and the base of the NPN, which is at the same time the junction between the base and the collector of the PNP. The gate connects to the base of the initial NPN, and when it is pulled high, the transistor is operating in the "active" region, with significant collector-emitter voltage, and thus high beta. Y Ok, but I think that what you say about the active region is right only during the turn-on process, when the voltage across the two latching transistor is equal to the off-state voltage. After the turn-on process has ended, I think that neither transistor can be in active the region, or at most only one of the two (the other being in saturation): if both were in the forward active region, the would have β≫1, but since the collector of Q1 is the base of Q2, you would have $I_{C2}=\beta _{2}I_{B2}=\beta _{2}I_{C1}=\beta _{2}\beta _{1}I_{B1}$ ; but the collector of Q2 (NPN) is also the base of Q1 (PNP) and therefore $I_{C2}=\beta _{2}\beta _{1}I_{B1}=I_{B1}$ , which means that $\beta _{2}\beta _{1}=1$ , but this is not consistent with our starting hypothesis that both transistors were in the active region. Thus, at least one of the two transistors must be in saturation, and since the VCE of a saturated BJT is typically no more than 0.3V (the VBE(sat), on the other hand, is typically over 0.8V), from a designer's point of view it is better to have both the transistors in saturation in order to get a lower voltage drop between MT1 and MT2, so they maybe try to design both transistors in such a way, I think.

In Q-IV, the main current path is A1-PNPN-A2(−). The two PN junctions have Vbe forward drops across them, and the NP junction is the collector-base junction of the two transistors, and holds the standoff voltage. Y

The gate connects to the base of a separate NPN, whose emitter is also A1, and whose collector is the base of the PNP. ~~When~~ Immediately after you put current across this transistor's base-emitter junction (by raising the gate one Vbe above A1), i.e. at the start of the turn-on process, the collector voltage is one diode drop less than A1. Y I agree, but only if you put into the text the two slight clarifications I have made. ~~(As mentioned before, this is a lot less than 0.7V, in fact almost 0V, because the forward current is almost zero.)~~ N During the turn-on process, the "collector" of the NPN transistor is at near-zero potential because the transistor is saturated, not because current is low. In fact, remember that Q-IV needs the largest gate current among the four quadrants to turn on, and it can be in the order of tens of milliamps. Moreover, it is important to notice that in Q-III and Q-IV the voltage during the off-state drops accross the junction between the "central" n-layer and the lower p-layer of figure 6:

This is deep in the saturation region, Y Yeah! where a transistor's effective beta is greatly reduced. Does it make sense to talk about β in the saturation mode? The main thyristor is triggered identicially to Q-III, but with the collector current of this transistor rather than the gate current directly. It never was a high-beta transistor to start with, and now it's trying to operate with a slightly "reversed" Vce, reducing it to something less than unity. Thus, the Q-IV triggering current is more than the Q-III triggering current. N Actually, the only difference I can notice between the two triggering modes (Q-III and Q-IV) is their different distance from the final current path. Please compare the description of Q-III and Q-IV in the main article.

So, just to summarize, I think that the key points of the issue are the following facts:

the triggering process in Q-IV starts with a transistor which is in saturation from the beginning of its operation, so you have to drive more current into the gate to have it turned on because you cannot use the transistor's current amplification capability;
in Q-IV, the turn-on process begins farther from the final PNPN main conducting structure than in Q-III: this is not something secondary in importance, because at the beginning of the turn on process you have to lower the voltage of the large central n-layer by diffusing into it electrons from the MT1 terminal through a saturated transistor. Those electrons are diffusing against the voltage potential, which tends to attract them back into the upper p-layer (see the figure I put above), so if you want them to reach that region of the central n-layer where the final conduction takes place you have to offset the electrons which escape back by driving more gate current than in Q-III.

This is my opinion about why Q-IV is the most unfavorable of the four triggering modes. I unfortunately haven't found references to confirm it yet and it seems quite hard to find an explanation to this issue in literature. —Vitaltrust (talk) 19:39, 29 April 2012 (UTC)

First of all, thank you for a very interesting and enlightening discussion! I'm about to disagree with you, but I don't want to appear irritated or short-tempered. Like you, I haven't found a good reference explaining this and I'm having fun working it out. The following is what I think is happening, but I won't be sure until iy makes sense to someone else as well.

Ok, but I think that what you say about the active region is right only during the turn-on process, when the voltage accross the two latching transistor is equal to the off-state voltage Y Yes; I had intended that to be obvious. I am only taking about the initial triggering of the TRIAC; once the current through the main terminals is sufficient to collapse the voltage across the TRIAC, the gate is no longer relevant.

After the turn-on process has ended, I think that neither transistor can be in active the region, or at most only one of the two (the other being in saturation) N I think you'll find that both transistors are on the edge of saturation, but technically in the active region. The definition of the boundary is when the collector-base voltage is zero (Vbe = Vce), and whatever happens inside the thyristor, there has to be a monotone voltage gradient across the PNPN stack. So the PNP's collector is a lower voltage than its base, and similarly the NPN's collector is at a higher voltage than its base.. Now, what happens is that the collector voltage drops until the beta drops to the point that the product of the current gains equals 1, so it's not in the normal "high beta" active region. Your math is absolutely right, and thinking in terms of saturation is better, but technically both are active. (To quote Bipolar junction transistor#Regions of operation: "Although these regions are well defined for sufficiently large applied voltage, they overlap somewhat for small (less than a few hundred millivolts) biases.")

During the turn-on process, the "collector" of the NPN transistor is at near-zero potential because the transistor is saturated, not because current is low. N While we can argue about the direction of the cause and effect arrow (are raindrops falling because it is raining, or is it raining because raindrops are falling?), the potential is zero before turn-on starts, because the current is low. Turning on (adding gate current) doesn't change that, but does change the base voltage, which then establishes the conditions for saturation (base voltage higher than collector voltage). Because the collector voltage was low before the saturation condition was established, I have a hard time saying that the former happened because of the latter.

Does it make sense to talk about β in the saturation mode? Absolutely! It's simply the ratio of collector current to base current, so it's defined whenever base current is non-zero.

Actually, the only difference I can notice between the two triggering modes (Q-III and Q-IV) is their different distance from the final current path. Please compare the description of Q-III and Q-IV in the main article. N Whoa! I certainly agree that there are strong similarities due to the same final current path, but there's a huge difference! It's the same in that an NPN separate from the final current path injects current into the base of the "main" PNP, but note the differences:

In Q-III, the gate is the emitter of an NPN, which is in saturation when triggered, but only slightly. Vce and Vbe are both positive, and almost the same (although Vbe is higher, since the collector is one low-current diode drop lower than the base).
In Q-IV, the gate is the base, and Vce is not only zero, it's actually slightly negative. This is nowhere near the edge of saturation.

Now I'm curious what you'll find laughably wrong about what I've written! 71.41.210.146 (talk) 07:11, 1 May 2012 (UTC)

Hi! Well, first of all, I would like to thank you too for this interesting discussion. I don't know if our talk is going towards the right direction, since we haven't found any sources to confirm either opinion so far, unfortunately. But nevertheless it is a good brain-training and for me also an occasion to take a look again to some concepts I studied when I was at the university, some years ago...

First of all, regarding this paragraph:

During the turn-on process, the "collector" of the NPN transistor is at near-zero potential because the transistor is saturated, not because current is low. N While we can argue about the direction of the cause and effect arrow (are raindrops falling because it is raining, or is it raining because raindrops are falling?), the potential is zero before turn-on starts, because the current is low. Turning on (adding gate current) doesn't change that, but does change the base voltage, which then establishes the conditions for saturation (base voltage higher than collector voltage). Because the collector voltage was low before the saturation condition was established, I have a hard time saying that the former happened because of the latter.

Ok, written in these words, I agree. Maybe there was some misunderstanding between us on this point.

Saturation

Regarding your statement about the operation mode of the two latching resistors, as I told you, if Math isn't an opinion they must have

\beta _{1}\beta _{2}=1

, so they cannot be both in the forward active region (unless they have both β=1 by design, which seems quite odd). Obviously, this seems to imply that the voltage accross the device is not monotone, but has it necessarily to be? We have two latching transistor, not a resistor, so I don't see a non-monotone voltage pattern as something impossible. When I was a postgraduate student, I remember I designed a net with two transistor in a similar fashion (I used them to memorize a safety condition in a boost PFC circuit) and they were in saturation: once triggered, the base of the pnp is kept at a low voltage by the current dragged by the collector of the npn and, vicecersa, the base of the npn is kept high by the collector of the pnp. So I don't agree on this matter, but on the other hand I think it is something not very important: I hope none of us doubts that the two transistors keep each other turned on.

Beta

Beware that, to be strict, β isn't simply

I_{C}/I_{B}

, but instead it is a specific constant of a particular transistor, so it is not so straightforward to talk about β in the saturation mode. If we go into the physics of the device, you get this interesting formula as a direct consequence of the Ebers-Moll model for a npn transistor:

I_{C}=\beta I_{B}-I_{CEO}\left(e^{\frac {V_{BC}}{V_{T}}}-1\right)

In this formula, ICEO is the current flowing from the collector to the emitter with the base shorted to the emitter and a reverse-biased base-to-emitter junction (VBC < 0), so it is very low; VT is the so-called "thermal voltage", which is about 25-26mV at 30°C. You can find a proof here, but the document is in Italian. As soon as I find something similar in English, I will update the link.

In the previous expression,

\beta =I_{C}/I_{B}

only if VBC > 0, i.e. in the forward active mode. When in saturation, VBC < 0 and so IC < βIB.

Q-III and Q-IV

I agree that in Q-III the gate of the TRIAC works as an emitter whereas in Q-IV it works as a base, but in Q-IV VBE is positive and VBC is positive too: isn't this saturation? Of course, in Q-IV it is saturated from the beginning, while in Q-III it gets saturated "just after" the beginning, but I am not sure that this alone can account for a higher threshold current. I think that most of the reason lies in the distance between the triggering npn transistor and the final current path, which in Q-III is less than in Q-IV: it is known that diffusion accounts for the greatest part of the current in a semiconductor, so my guess is that the electrons injected into the central n-layer tend to return back into the upper p-layer (where they are minority carriers) before reaching the latching region of this operation mode.

I hope someone finds a reliable source soon in order to clear any doubt.