Wikipedia:Reference desk/Archives/Computing/2024 August 4

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August 4

Karnaugh map/gates

As of now, is the 'or' gate better at handling electricity vs the 'and' gate?Afrazer123 (talk) 01:29, 4 August 2024 (UTC)

That will depend on the implementation, and what electrical state represents the 0 or 1. And it also depends on what you mean by "better". (faster, less energy wasted, smaller, least noise, least sensitive to noise, fan out, tolerance of power supply variation, cheaper, higher yield). Graeme Bartlett (talk) 10:47, 4 August 2024 (UTC)

Yes. The Karnaugh map is useful for showing logical relations between Boolean data types that take only values "1" (true) or "0" (false). Elementary Logic gate functions such as AND, OR, NAND, NOR, EXOR, etc. can be mapped, also combinations of connected gates if they are not too complicated. However Boolean data is abstract and the "1" and "0" need not always correspond to electric voltages. Karnaugh maps are equally applicable to fluid logic that uses water instead of electricity. For example a fluid OR gate is simply two pipes being merged. Philvoids (talk) 17:15, 4 August 2024 (UTC)

"better": less energy wasted, higher yield. Afrazer123 (talk) 05:52, 5 August 2024 (UTC)

CMOS (Complementary metal–oxide–semiconductor) logic devices have low static power consumption and do not produce as much waste heat as other forms of logic, like NMOS logic or Transistor–transistor logic (TTL), which normally have some standing current even when not changing state. Since one transistor of the MOSFET pair is always off, the series combination draws significant power only momentarily during switching between on and off states. There is no significant difference between power consumptions of the logic functions AND, OR, etc. The current drawn from the supply increases with increasing rate of data changes and is mainly due to charging and discharging the output capacitance. Philvoids (talk) 13:14, 5 August 2024 (UTC)

Thanks, I read about the clock rate or clock speed. I think it adds to the logic your reply. Afrazer123 (talk) 21:20, 6 August 2024 (UTC)

For actual numbers, old digital circuits that I used back in the 70s implemented both and and or with components. The drop is 0.3v pretty much any way you do it for both an or and an and gate. You are either dropping 0.3v across a diode or 0.3v across a transistor. I doubt any modern circuits have that much drop and I'm certain it is still very similar between diodes and transistors. 12.116.29.106 (talk) 12:20, 6 August 2024 (UTC)

Modern CMOS gates don't have diodes, nor do the MOS transistors have saturation voltage drops of the sort you're talking about. Dicklyon (talk) 03:53, 8 August 2024 (UTC)

"As of now" means CMOS, one would presume. The "elementary" gates are inverting: NAND and NOR. One has a marginally better energy per operation than the other, but not so much that you'd worry about it. And it depends on your logic conventions, which you can change in midstream if that helps. Back in the NMOS days, with positive logic (higher voltage representing logic 1), the NOR gate had a signficantly better energy per operation than the NAND gate, due to the use of N-type switches to ground and passive pullups, with switches being in series for NAND and parallel for NOR. And both were better than PMOS gates, due to the higher mobility of electrons compared to holes. But CMOS is more nearly symmetric (at least in the most typical logic gate circuits). I think the one with series N-type and parallel P-type devices is a bit better (that's a NAND for positive logic); but I wouldn't swear to it. Choosing NAND vs NOR is not a big deal compared to using AOI (AND-OR-invert) gates and optimizations at other levels. One such other technique is the use of dynamic logic, which gets more complicated to reason about, but still probably the gates with parallel switches are a bit more energy efficient than the ones with series switches. But other considerations dominate. And I haven't seen anyone use Karnaugh maps in the last 4 decades; are they still teaching those? Dicklyon (talk) 03:53, 8 August 2024 (UTC)

Around 2003, I was taught about Karnaugh maps at a community college. In 2004, I submitted such information on an application to a summer internship. My task there was to program the Fourier transform using machine language. A spreadsheet called Excel, with

its built-in trig. functions, was used too. "The Fourier transform relates the time domain, in red, with a function in the domain of the frequency, in blue." An illustration of this is shown in Wikipedia under Fourier transform. There were constraints because of the fact that a negative to positive infinity summation couldn't be done because of the computer's counting limitations as far as I know. I have brought up the question of a complex analysis. Thanks Afrazer123 (talk) 23:01, 8 August 2024 (UTC)

Well, it's not related to Karnaugh maps. And yes computers are not well matched to infinite problems like the Fourier transform, but are good for the discrete Fourier transform, especially implemented via the fast Fourier transform. Maybe that's what you were intended to do for your internship project. I did that once, in 1974, using assembly code on an HP 2116B. Not hard. Dicklyon (talk) 04:09, 10 August 2024 (UTC)

I would say that my 'logic conventions' regarding the NAND and NOR gates come from the source code or the assembly code with registers. The CPU's main memory was sufficient. It was intriguing reading about CMOS too. "CMOS is more nearly symmetric (at least in the most typical logic gate circuits)." One practical application of the DFT is the "daily temperature readings, sampled over a finite time interval (often defined by a window function)." Window functions are typically "bell shaped" curves. Finally, I delved into my summer task and thanks for your very informative reply. Afrazer123 (talk) 06:26, 10 August 2024 (UTC)

You can't tell anything about the underlying logic/voltage conventions from source code, or from logic diagrams even. You need to see the circuits that implement the gates, or have an explicit statement of the convention (e.g. high voltage = 1, low voltage = 0, which is most typical). And you definitely need to see circuits, and probably also some of their parameters, to begin to answer your original question; though the answer "about the same" is probably correct enough in general. Dicklyon (talk) 14:40, 10 August 2024 (UTC)

By the way, the Apollo Guidance Computer#Logic hardware used only one type of small-scale chip: a dual 3-input NOR. Dicklyon (talk) 04:03, 8 August 2024 (UTC)