This is the talk page for discussing improvements to the Duncan's taxonomy article. This is not a forum for general discussion of the article's subject.
This article is within the scope of WikiProject Computing, a collaborative effort to improve the coverage of computers, computing, and information technology on Wikipedia. If you would like to participate, please visit the project page, where you can join the discussion and see a list of open tasks.ComputingWikipedia:WikiProject ComputingTemplate:WikiProject ComputingComputing articles
Latest comment: 13 years ago3 comments2 people in discussion
{{Request edit}}
// Don't know who created this page but I'd like to fill in the actual taxonomy (computer architecture class definitions),
// since I've recently returned to the field. Am hoping neutrality will speak for itself but both that and accuracy can be checked
// against the original article (ref#2).
// Please consider adding the definitions below for the three highest-level categories in the taxonomy.
// under heading "Synchronous Architectures"
This category includes all the parallel architectures that coordinate concurrent execution in lockstep fashion and do so via mechanisms such as global clocks, central control units or vector unit controllers. Further subdivision of this category is made primarily on the basis of the synchronization mechanism.
// under heading "MIMD" (Flynn has already been cited via ref#1)
Based on Flynn's Multiple-Instruction-Multiple-Data Streams terminology, this category spans a wide spectrum of architectures in which processors execute mutiple instruction sequences on (potentially) dissimilar data streams without strict synchronization. Although both instruction and data streams can be different for each processor, they need not be. Thus, MIMD architectures can run identical programs that are in various stages at any given time, run unique instruction and data streams on each processor or execute a combination of each these scenarios. This category is subdivided further primarily on the basis of memory organization.
// under heading "MIMD Paradigm" {a second pass can add the links to pages for each example}
The MIMD-Based Paradigms category subsumes systems in which a specific programming or execution paradigm is at least as fundamental
to the architectural design as structural considerations are. Thus, the design of dataflow architectures and reduction machines is as much the product of supporting their distinctive execution paradigm as it is a product of connecting processors and memories in MIMD fashion. The category's subdivisions are defined by these paradigms.
When you leave messages, please remember to "sign" your name, by putting ~~~~ (four tilde signs) at the end. This will add your name, and the date and time. You can also do this by clicking the 'sign' button, pictured to the right. — Preceding unsigned comment added by Rvduncanjr (talk • contribs) 05:32, 15 February 2011
I've added the above.
Please note, the most important thing - for all facts - is to give references, where the reader can check the facts.
For the first two above, I'm assuming that all the facts can be checked in the "Flynn" reference 2? So I used that same reference.
For the third part, for now, I was not sure.
It's essential to give references, because of the core policy of verifiability, and to avoid any original research or novel synthesis, both of which are not appropriate for an encyclopaedia.
So, in future, please make it very clear where each fact can be checked. If that means repeating the same reference many times, that's fine - but everything should have a footnote reference - otherwise it could be challenged and removed by other editors.
Please feel free to add further requests at the end of this page (in a new section), with another {{Request edit}}. Note, sometimes it can take many days for volunteers to process these requests; this time.
Done{{Request edit}}
First, thanks for doing this work and for your constructive suggestions.
WRT references -- at the risk of seeming ungrateful -- please change the references you added from referring to item 2 [Flynn] to item [1], my 1990 article that defines the taxonomy. The entire page is merely stating what the taxonomy categories are, as they appeared in a single article in Computer magazine. Thus, every assertion I make about the taxonomy's categories refer to that article and can be verified by referring to it. (Note that I make no remarks of opinion about the taxonomy's relative goodness, etc.) As background -- Flynn's 1966 piece is not a fully articulated taxonomy (classification system); it simply defines 4 categories of computing, including the familiar MIMD & SIMD monikers (as well as the seldom-used MISD and SISD). It's reasonable to reference Flynn the first time that the SIMD and MIMD abbreviations are used but otherwise it wouldn't make much sense. There. Let's hope that my own verbiage here(in contrast) does make some sense. ;) Thanks again -- and this time I have remembered to add the 4 tildes.
Rvduncanjr (talk) 17:58, 15 February 2011 (UTC)Reply
I think I understand, yes. I changed the reference for the first two sections, to ref 1. I also added the ref to the "MIMD-paradigm Architectures" section, because I believe that is covered. Hope that is OK. Thanks again, Chzz ► 16:20, 16 February 2011 (UTC)Reply
Latest comment: 13 years ago4 comments3 people in discussion
{{Request edit}}
Chzz. Thought I should give you a break for awhile! I'd like to add the material for systolic arrays (subsection under the Synchronous class). Still getting the feel of the wiki editing language but here goes below.
BTW you can see a PDF of my original article (so you'll know if I'm quoting it correctly). ;) It is available here:
http://web.cecs.pdx.edu/~alaa/ece588/papers/duncan_ieeecomputer_1990.pdf
Systolic arrays, proposed during the 1980s[1] are multiprocessors in which data and partial results are rhythmically pumped from processor to processor through a regular, local interconnection network[2]. Systolic architectures use a global clock and explicit timing delays to synchronize data flow from processor to processor[2]. Each processor in a systolic system executes an invariant sequence of instructions before data and results are pulsed to neighboring processors[1].
Hi. Yes, mark-up was fine. No problem. I added it.
The only complaint I have is, you put literally {{tn|Request edit}} instead of just {{Request edit}}. The 'tn' part is to cancel out the template, once it has been done - so if you put that, it doesn't alert anyone to do it.
But fortunately, I'd made a note and checked back here anyway.
{{Request edit}}
Chzz. Thanks for the pointers on Request-edit. When you have a chance, please help with the vector architecture material.
I'd appreciate changing the section name from 'Vector' to 'Pipelined Vector Processors' -- this matches the article's text (rather than one terse figure's contents) and is clearer. Here's the proposed text for that section.
Pipelined vector processors are characterized by pipelined functional units that accept a sequential stream of array or vector elements, such that different stages in a filled pipeline are processing different elements of the vector at a given time[3]. Parallelism is provided both by the pipelining in individual functional units described above, as well as by operating multiple units of this kind in parallel and by chaining the output of one unit into another unit as input[3].
Vector architectures that stream vector elements into functional units from special vector registers are termed register-to-register architectures, while those that feed functional units from special memory buffers are designated as memory-to-memory architectures[2]. Early examples of register-to-register architectures from the 1960s and early 1970s include the Cray-1[4] and Fujitsu VP-200, while the Control Data Cyber 205 and Texas Instruments Advanced Scientific Computer[5] are early examples of memory-to-memory vector architectures.
The late 1980s and early 1990s saw the introduction of vector architectures, such as the Cray Y-MP/4 and Nippon Electric Corporation SX-3 that supported 4-10 vector processors with a shared memory (see NEC SX architecture).
Chzz, please let me know if I'm properly using the double square brackets to vector readers to Wiki articles.
As always, thanks.
Rvduncanjr (talk) 03:37, 7 March 2011 (UTC)Reply
Latest comment: 13 years ago2 comments2 people in discussion
{{edit semi-protected}}
<Chzzz or other editor: here's the proposed text for the SIMD section. Since this serves as an intermediate class in this scheme, this is a brief description.>
This scheme uses the SIMD (Single Instruction Stream, Multiple Data Stream) category from Flynn's Taxonomy as a root class for Processor Array and Associative Memory subclasses. SIMD architectures[1] are characterized by having a control unit broadcast a common instruction to all processing elements, which execute that instruction in lockstep on diverse operands from local data. Common features include the ability for individual processors to disable an instruction and the ability to propagate instruction results to immediate neighbors over an interconnection network.
Rvduncanjr (talk) 17:43, 19 March 2011 (UTC)Reply
^ Michael Jurczyk and Thomas Schwederski,"SIMD-Processing: Concepts and Systems", pp. pp 649-679 in Parallel and Distributed Computing Handbook, A. Zomaya, ed., McGraw-Hill, 1996.
Done
{{Request edit}}
First, thanks for doing this work and for your constructive suggestions.
WRT references -- at the risk of seeming ungrateful -- please change the references you added from referring to item 2 [Flynn] to item [1], my 1990 article that defines the taxonomy. The entire page is merely stating what the taxonomy categories are, as they appeared in a single article in Computer magazine. Thus, every assertion I make about the taxonomy's categories refer to that article and can be verified by referring to it. (Note that I make no remarks of opinion about the taxonomy's relative goodness, etc.) As background -- Flynn's 1966 piece is not a fully articulated taxonomy (classification system); it simply defines 4 categories of computing, including the familiar MIMD & SIMD monikers (as well as the seldom-used MISD and SISD). It's reasonable to reference Flynn the first time that the SIMD and MIMD abbreviations are used but otherwise it wouldn't make much sense. There. Let's hope that my own verbiage here(in contrast) does make some sense. ;) Thanks again -- and this time I have remembered to add the 4 tildes.
Rvduncanjr (talk) 17:58, 15 February 2011 (UTC)