Wikipedia

Tensor Processing Unit

This article is about the chip developed by Google. For the smartphone system-on-chip, see Google Tensor. For other devices that provide tensor processing for artificial intelligence, see AI accelerator.

Tensor Processing Unit (TPU) is an AI accelerator application-specific integrated circuit (ASIC) developed by Google for neural network machine learning, using Google's own TensorFlow software.[2] Google began using TPUs internally in 2015, and in 2018 made them available for third-party use, both as part of its cloud infrastructure and by offering a smaller version of the chip for sale.

Tensor Processing Unit
Tensor Processing Unit 3.0
DesignerGoogle
Introduced2015[1]
TypeNeural network
Machine learning

Comparison to CPUs and GPUs

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Compared to a graphics processing unit, TPUs are designed for a high volume of low precision computation (e.g. as little as 8-bit precision)[3] with more input/output operations per joule, without hardware for rasterisation/texture mapping.[4] The TPU ASICs are mounted in a heatsink assembly, which can fit in a hard drive slot within a data center rack, according to Norman Jouppi.[5]

Different types of processors are suited for different types of machine learning models. TPUs are well suited for CNNs, while GPUs have benefits for some fully-connected neural networks, and CPUs can have advantages for RNNs.[6]

History

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The tensor processing unit was announced in May 2016 at Google I/O, when the company said that the TPU had already been used inside their data centers for over a year.[5][4] Google's 2017 paper describing its creation cites previous systolic matrix multipliers of similar architecture built in the 1990s.[7] The chip has been specifically designed for Google's TensorFlow framework, a symbolic math library which is used for machine learning applications such as neural networks.[8] However, as of 2017 Google still used CPUs and GPUs for other types of machine learning.[5] Other AI accelerator designs are appearing from other vendors also and are aimed at embedded and robotics markets.

Google's TPUs are proprietary. Some models are commercially available, and on February 12, 2018, The New York Times reported that Google "would allow other companies to buy access to those chips through its cloud-computing service."[9] Google has said that they were used in the AlphaGo versus Lee Sedol series of human-versus-machine Go games,[4] as well as in the AlphaZero system, which produced Chess, Shogi and Go playing programs from the game rules alone and went on to beat the leading programs in those games.[10] Google has also used TPUs for Google Street View text processing and was able to find all the text in the Street View database in less than five days. In Google Photos, an individual TPU can process over 100 million photos a day.[5] It is also used in RankBrain which Google uses to provide search results.[11]

Google provides third parties access to TPUs through its Cloud TPU service as part of the Google Cloud Platform[12] and through its notebook-based services Kaggle and Colaboratory.[13][14]

Products

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Tensor Processing Unit products[15][16][17]
TPUv1 TPUv2 TPUv3 TPUv4[16][18] TPUv5e[19] TPUv5p[20] [21] v6e (Trillium)[22][23]
Date introduced 2015 2017 2018 2021 2023 2023 2024
Process node 28 nm 16 nm 16 nm 7 nm Unstated Unstated
Die size (mm2) 331 < 625 < 700 < 400 300-350 Unstated
On-chip memory (MiB) 28 32 32 32 48 112
Clock speed (MHz) 700 700 940 1050 Unstated 1750
Memory 8 GiB DDR3 16 GiB HBM 32 GiB HBM 32 GiB HBM 16 GB HBM 95 GB HBM 32 GB
Memory bandwidth 34 GB/s 600 GB/s 900 GB/s 1200 GB/s 819 GB/s 2765 GB/s 1640 GB/s
TDP (W) 75 280 220 170 Not Listed Not Listed
TOPS (Tera Operations Per Second) 23 45 123 275 197 (bf16)

393 (int8)

459 (bf16)

918 (int8)

918 (bf16)

1836 (int8)

TOPS/W 0.31 0.16 0.56 1.62 Not Listed Not Listed

First generation TPU

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The first-generation TPU is an 8-bit matrix multiplication engine, driven with CISC instructions by the host processor across a PCIe 3.0 bus. It is manufactured on a 28 nm process with a die size ≤ 331 mm2. The clock speed is 700 MHz and it has a thermal design power of 28–40 W. It has 28 MiB of on chip memory, and 4 MiB of 32-bit accumulators taking the results of a 256×256 systolic array of 8-bit multipliers.[7] Within the TPU package is 8 GiB of dual-channel 2133 MHz DDR3 SDRAM offering 34 GB/s of bandwidth.[17] Instructions transfer data to or from the host, perform matrix multiplications or convolutions, and apply activation functions.[7]

Second generation TPU

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The second-generation TPU was announced in May 2017.[24] Google stated the first-generation TPU design was limited by memory bandwidth and using 16 GB of High Bandwidth Memory in the second-generation design increased bandwidth to 600 GB/s and performance to 45 teraFLOPS.[17] The TPUs are then arranged into four-chip modules with a performance of 180 teraFLOPS.[24] Then 64 of these modules are assembled into 256-chip pods with 11.5 petaFLOPS of performance.[24] Notably, while the first-generation TPUs were limited to integers, the second-generation TPUs can also calculate in floating point, introducing the bfloat16 format invented by Google Brain. This makes the second-generation TPUs useful for both training and inference of machine learning models. Google has stated these second-generation TPUs will be available on the Google Compute Engine for use in TensorFlow applications.[25]

Third generation TPU

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The third-generation TPU was announced on May 8, 2018.[26] Google announced that processors themselves are twice as powerful as the second-generation TPUs, and would be deployed in pods with four times as many chips as the preceding generation.[27][28] This results in an 8-fold increase in performance per pod (with up to 1,024 chips per pod) compared to the second-generation TPU deployment.

Fourth generation TPU

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On May 18, 2021, Google CEO Sundar Pichai spoke about TPU v4 Tensor Processing Units during his keynote at the Google I/O virtual conference. TPU v4 improved performance by more than 2x over TPU v3 chips. Pichai said "A single v4 pod contains 4,096 v4 chips, and each pod has 10x the interconnect bandwidth per chip at scale, compared to any other networking technology.”[29] An April 2023 paper by Google claims TPU v4 is 5-87% faster than an Nvidia A100 at machine learning benchmarks.[30]

There is also an "inference" version, called v4i,[31] that does not require liquid cooling.[32]

Fifth generation TPU

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In 2021, Google revealed the physical layout of TPU v5 is being designed with the assistance of a novel application of deep reinforcement learning.[33] Google claims TPU v5 is nearly twice as fast as TPU v4,[34] and based on that and the relative performance of TPU v4 over A100, some speculate TPU v5 as being as fast as or faster than an H100.[35]

Similar to the v4i being a lighter-weight version of the v4, the fifth generation has a "cost-efficient"[36] version called v5e.[19] In December 2023, Google announced TPU v5p which is claimed to be competitive with the H100.[37]

Sixth generation TPU

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In May 2024, at the Google I/O conference, Google announced TPU v6, which became available in preview in October 2024.[38] Google claimed a 4.7 times performance increase relative to TPU v5e,[39] via larger matrix multiplication units and an increased clock speed. High bandwidth memory (HBM) capacity and bandwidth have also doubled. A pod can contain up to 256 Trillium units.[40]

Edge TPU

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In July 2018, Google announced the Edge TPU. The Edge TPU is Google's purpose-built ASIC chip designed to run machine learning (ML) models for edge computing, meaning it is much smaller and consumes far less power compared to the TPUs hosted in Google datacenters (also known as Cloud TPUs[41]). In January 2019, Google made the Edge TPU available to developers with a line of products under the Coral brand. The Edge TPU is capable of 4 trillion operations per second with 2 W of electrical power.[42]

The product offerings include a single-board computer (SBC), a system on module (SoM), a USB accessory, a mini PCI-e card, and an M.2 card. The SBC Coral Dev Board and Coral SoM both run Mendel Linux OS – a derivative of Debian.[43][44] The USB, PCI-e, and M.2 products function as add-ons to existing computer systems, and support Debian-based Linux systems on x86-64 and ARM64 hosts (including Raspberry Pi).

The machine learning runtime used to execute models on the Edge TPU is based on TensorFlow Lite.[45] The Edge TPU is only capable of accelerating forward-pass operations, which means it's primarily useful for performing inferences (although it is possible to perform lightweight transfer learning on the Edge TPU[46]). The Edge TPU also only supports 8-bit math, meaning that for a network to be compatible with the Edge TPU, it needs to either be trained using the TensorFlow quantization-aware training technique, or since late 2019 it's also possible to use post-training quantization.

On November 12, 2019, Asus announced a pair of single-board computer (SBCs) featuring the Edge TPU. The Asus Tinker Edge T and Tinker Edge R Board designed for IoT and edge AI. The SBCs officially support Android and Debian operating systems.[47][48] ASUS has also demonstrated a mini PC called Asus PN60T featuring the Edge TPU.[49]

On January 2, 2020, Google announced the Coral Accelerator Module and Coral Dev Board Mini, to be demonstrated at CES 2020 later the same month. The Coral Accelerator Module is a multi-chip module featuring the Edge TPU, PCIe and USB interfaces for easier integration. The Coral Dev Board Mini is a smaller SBC featuring the Coral Accelerator Module and MediaTek 8167s SoC.[50][51]

Pixel Neural Core

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Main article: Pixel Neural Core

On October 15, 2019, Google announced the Pixel 4 smartphone, which contains an Edge TPU called the Pixel Neural Core. Google describe it as "customized to meet the requirements of key camera features in Pixel 4", using a neural network search that sacrifices some accuracy in favor of minimizing latency and power use.[52]

Google Tensor

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Main article: Google Tensor

Google followed the Pixel Neural Core by integrating an Edge TPU into a custom system-on-chip named Google Tensor, which was released in 2021 with the Pixel 6 line of smartphones.[53] The Google Tensor SoC demonstrated "extremely large performance advantages over the competition" in machine learning-focused benchmarks; although instantaneous power consumption also was relatively high, the improved performance meant less energy was consumed due to shorter periods requiring peak performance.[54]

Lawsuit

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In 2019, Singular Computing, founded in 2009 by Joseph Bates, a visiting professor at MIT,[55] filed suit against Google alleging patent infringement in TPU chips.[56] By 2020, Google had successfully lowered the number of claims the court would consider to just two: claim 53 of US 8407273  filed in 2012 and claim 7 of US 9218156  filed in 2013, both of which claim a dynamic range of 10-6 to 106 for floating point numbers, which the standard float16 cannot do (without resorting to subnormal numbers) as it only has five bits for the exponent. In a 2023 court filing, Singular Computing specifically called out Google's use of bfloat16, as that exceeds the dynamic range of float16.[57] Singular claims non-standard floating point formats were non-obvious in 2009, but Google retorts that the VFLOAT[58] format, with configurable number of exponent bits, existed as prior art in 2002.[59] By January 2024, subsequent lawsuits by Singular had brought the number of patents being litigated up to eight. Towards the end of the trial later that month, Google agreed to a settlement with undisclosed terms.[60][61]

See also

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References

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  1. ^ Jouppi et al, 2017, "In-Datacenter Performance Analysis of a Tensor Processing Unit", https://arxiv.org/abs/1704.04760
  2. ^ "Cloud Tensor Processing Units (TPUs)". Google Cloud. Retrieved 20 July 2020.
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  57. ^ "SINGULAR COMPUTING LLC, Plaintiff, v. GOOGLE LLC, Defendant: Amended Complaint for Patent Infringement" (PDF). rpxcorp.com. RPX Corporation. 2020-03-20. Retrieved 2024-01-10.
  58. ^ Wang, Xiaojun; Leeser, Miriam (2010-09-01). "VFloat: A Variable Precision Fixed- and Floating-Point Library for Reconfigurable Hardware". ACM Transactions on Reconfigurable Technology and Systems. 3 (3): 1–34. doi:10.1145/1839480.1839486. Retrieved 2024-01-10.
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